Driving circuit with slew-rate enhancement circuit

A driving circuit, comprising:

• an operational amplifier comprising a positive input terminal receiving an input voltage and a negative input terminal coupled to an output terminal of the operational amplifier for outputting an output voltage;
• a PMOS transistor comprising a first source terminal coupled to a high voltage source providing a high voltage, a first gate terminal coupled to a first node of the operational amplifier, and a first drain terminal coupled to the output terminal of the operational amplifier;
• an NMOS transistor comprising a second source terminal coupled to a low voltage source that is grounded, a second gate terminal coupled to a second node of the operational amplifier, and a second drain terminal coupled to the output terminal of the operational amplifier;
• and
• a driving auxiliary circuit receiving the input voltage and the output voltage and coupled to the first node and the second node, wherein the driving auxiliary circuit pulls down the voltage level of the first node and second node to a first voltage level when the input voltage exceeds the output voltage, and the driving auxiliary circuit pulls up the voltage level of the first node and second node to a second voltage level when the output voltage exceeds the input voltage.