Semiconductor device
AssigneeElpida Memory, Inc.
InventorHideyuki Yoko
Life of this patent
Estimating the term…
Abstract
One interface chip and a plurality of core chips are electrically connected via a plurality of through silicon vias. A data signal of a driver circuit is input into the core chip via any one of the through silicon vias. An output switching circuit activates any one of tri-state inverters and selects one of the through silicon vias. The tri-state inverters amplify the data signal and transmit it to the through silicon via. Similarly, an input switching circuit activates any one of tri-state inverters. These tri-state inverters also amplify the data signal transmitted from the through silicon via and supply it to the receiver circuit.
Claims17
A semiconductor device comprising:
- a first semiconductor chip that includes a driver circuit outputting a signal;
- a second semiconductor chip that includes a receiver circuit receiving the signal;
- and
- a plurality of through silicon vias that connect the first and second semiconductor chips, wherein
- the first semiconductor chip includes:
- a plurality of first tri-state inverters each coupled between the driver circuit and an associated one of the through silicon vias;
- and
- an output switching circuit that exclusively activates one of the first tri-state inverters to transmit the signal from the driver circuit to one of the through silicon vias, and
- the second semiconductor chip includes:
- a plurality of second tri-state inverters each coupled between the receiver circuit and an associated one of the through silicon vias;
- and
- an input switching circuit that exclusively activates one of the second tri-state inverters to transmit the signal from one of the through silicon vias to the receiver circuit.
A semiconductor device comprising:
- first and second semiconductor chips laminated to each other;
- and
- a plurality of through silicon vias that penetrates one of the first and second semiconductor chips, wherein
- the first semiconductor chip includes:
- an output circuit having an output node;
- a plurality of first circuits each having an input node coupled to the output node of the output circuit and an output node coupled to an associated one of the through silicon vias, each of the output nodes of first circuits takes one of a first logic level, a second logic level and a high impedance state;
- and
- an output switching circuit that controls the first circuits such that one of the output nodes of the first circuits takes one of the first and second logic level and other of the output nodes of the first circuits takes the high impedance state, and
- the second semiconductor chip includes:
- an input circuit having an input node;
- a plurality of second circuits each having an input node coupled to an associated one of the through silicon vias and an output node coupled to the input node of the input circuit;
- and
- an input switching circuit that activates one of the second circuits.
A semiconductor device comprising:
- first and second semiconductor chips laminated to each other;
- and
- a plurality of through silicon vias that penetrates one of the first and second semiconductor chips, wherein
- the first semiconductor chip includes:
- an output circuit having an output node;
- a plurality of first circuits each having an input node coupled to the output node of the output circuit and an output node coupled to an associated one of the through silicon vias;
- and
- an output switching circuit that activates one of the first circuits, and
- the second semiconductor chip includes:
- an input circuit having an input node;
- a plurality of second circuits each having an input node coupled to an associated one of the through silicon vias and an output node coupled to the input node of the input circuit, each of the output nodes of second circuits takes one of a first logic level, a second logic level and a high impedance state;
- and
- an input switching circuit that controls the second circuits such that one of the output nodes of the second circuits takes one of the first and second logic levels and other of the output nodes of the second circuits takes the high impedance state.
Dependencies are inferred from the claim text.