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US 2011/0084725 A1Published application
High speed multiple memory interface i/o cell
AssigneeLSI Corporation
InventorsDharmesh Bhakta, Hong-Him Lim, Cheng-Gang Kong, Todd Randazzo
Life of this patent
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Abstract
An input/output (I/O) cell including one or more driver-capable segments and one or more on-die termination (ODT) capable segments. The I/O cell may be configured as an output driver in a first mode and Thevenin equivalent termination in a second mode.
Claims9
A binary programmable predriver comprising:
- a data enable logic;
- an on-die termination (ODT) sequencer;
- a plurality of first drivers;
- and
- a plurality of second drivers.
2 more elements
A dynamic on-die termination sequencer comprising:
- a first circuit configured to generate a on-die termination mode control signal in response to an enable signal, a termination control signal and a data signal;
- and
- a second circuit configured to generate a driver mode control signal in response to the enable signal, the termination control signal and the data signal.
A calibration circuit comprising:
- a current steering digital-to-analog converter (DAC);
- a comparator;
- a plurality of first cascode pairs configured to adjust a slew rate of a p-channel;
- a plurality of second cascode pairs configured to adjust a slew rate of an n-channel;
- a p-channel on-die termination (ODT) network;
- and
- an n-channel ODT network.
4 more elements
Dependencies are inferred from the claim text.