Built-in Line Test Method

Abstract

A method for testing a line including an input/output pin of a programmable logic circuit, said line including at least one individual line extending from the input/output pin to a peripheral element, said input/output pin being able to be either at a high logic level or at a low logic level opposite to the high logic level. The method includes, between an initial driving instant and a final driving instant, a step for driving the input/output pin in which a driving voltage is applied to the terminals of the input/output pin. The method also includes: from the final driving instant, a step for measuring the level of the input/output pin during which the pin is no longer driven and during which the measured logic level is recorded for the input/output pin at least one measuring instant, and the measured logic level(s) is/are compared, at the (respective) measuring instant(s), with the theoretical logic level(s) at which the input/output pin should be at the (respective) measuring instant(s) in the absence of any line failure, and, when at least one logic level measured at a measuring instant differs from the theoretical logic level at said measuring instant, a line failure is detected.

Dependencies are inferred from the claim text.