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US 2011/0084722 A1Published application
Semiconductor device and test method thereof
AssigneeElpida Memory, Inc.
InventorNaohisa Nishioka
Life of this patent
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Abstract
A semiconductor device includes a plurality of memory chips arranged in a layered manner, each including a substrate and a memory cell array, and a plurality of current paths provided while penetrating through the memory chips. Each of the memory chips includes a test circuit that reads test data from a corresponding one of the memory cell array and outputs a layer test result signal responding to the test data to a different current path for each of the memory chips.
Claims12
A semiconductor device comprising:
- a plurality of semiconductor chips, each of the semiconductor chips including;
- a substrate including upper and lower surfaces;
- first to Mth upper terminals on the upper surface, where M is an integer;
- first to Mth lower terminals on the lower surface, the first to Mth lower terminals being vertically aligned with the first to Mth upper terminals, respectively;
- first to Mth electrodes each of which penetrates the substrate to reach the upper and lower surfaces,
- (1) the second to Mth electrodes being electrically coupled to the first to M-lth upper terminals, respectively,
- (2) the first electrode being electrically coupled to the Mth upper terminal, and
- (3) the first to Mth electrodes being electrically coupled to the first to Mth lower terminals, respectively;
- a memory cell array holding a plurality of test data;
- and
- a first test circuit coupled between the memory cell array and the first electrode, receiving the test data supplied from the memory cell array, performing a first logic operation on logic levels of the test data so as to generate a layer test result signal and supplying the layer test result signal to the first electrode, wherein
- the plurality of memory chips are stacked with each other such that the first to Mth upper terminals of a lower one of the semiconductor chips are electrically coupled respectively to the first to Mth lower terminal of an upper one of the semiconductor chips.
9 more elements
A semiconductor device comprising:
- a plurality of semiconductor chips stacked with each other, each of the semiconductor chips including;
- a memory cell array holding a plurality of test data, and
- a first test circuit coupled to the memory cell array, receiving the test data supplied from the memory cell array and performing a first logic operation on logic levels of the test data so as to generate a layer test result signal,
- an interface chip stacked with the semiconductor chips;
- and
- a plurality of current paths each transfers the layer test result signal of an associated one of the semiconductor chips to the interface chip.
3 more elements
A semiconductor device comprising:
- a plurality of memory chips laminated to each other, each of the memory chips including a semiconductor substrate and a memory cell array;
- and
- a plurality of current paths constituted by a plurality of through silicon vias that penetrate through the semiconductor substrate of each of the memory chips, wherein
- each of the memory chips includes a test circuit that outputs a layer test result signal obtained by compressing test data read from the memory cell array to a different one of the current paths for each of the memory chips.
1 more element
Dependencies are inferred from the claim text.