Programmable current mirror
AssigneesTaiwan Semiconductor Manufacturing Company, Ltd., Global Unichip Corporation
InventorsPo-Shing YU, Chia-Hsiang CHANG
Life of this patent
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Abstract
A programmable current mirror a reference transistor, first and second mirror transistors, and a first current bypass. The reference transistor has a source and a gate coupled to a reference current node. The first and second mirror transistors are coupled together in series at a first node. Each of the first and second mirror transistors having gates coupled to each other and to the gate of the reference transistor. The first current bypass including a switch disposed in parallel with the second mirror transistor. The first current bypass is coupled to a source and a drain of the second mirror transistor and to the first node.
Claims20
A programmable current mirror, comprising:
- a reference transistor having a source and a gate coupled to a reference current node;
- first and second mirror transistors coupled together in series at a first node, each of the first and second mirror transistors having gates coupled to each other and to the gate of the reference transistor;
- and
- a first current bypass including a switch disposed in parallel with the second mirror transistor, the first current bypass coupled to a source and a drain of the second mirror transistor and to the first node.
A programmable current mirror, comprising:
- a first reference transistor having a source and a gate coupled to a first node for receiving a reference current;
- first, second, third, and fourth mirror transistors coupled in series, the first and second mirror transistors coupled together at a second node, the second and third mirror transistors coupled together at a third node, the third and fourth transistors coupled together at a fourth node, each of the mirror transistors having respective gates coupled to each other and to the gate of the first reference transistor;
- and
- first, second, and third current bypasses, each bypass including a respective switch, the first current bypass coupled to the second and third nodes in parallel with the second mirror transistor, the second current bypass coupled to the third and fourth nodes in parallel with the third mirror transistor, the third current bypass coupled to the fourth node in parallel with the fourth mirror transistor.
A programmable current mirror, comprising:
- a plurality of reference transistors coupled in series, each of the reference transistors having gates coupled together and to a first reference current node;
- a plurality of mirror transistors coupled in series with each other, each of the mirror transistors having gates coupled together and to the gates of each of the plurality of reference transistors;
- and
- a respective current bypass coupled in parallel with each respective one of the reference and mirror transistors, each of the current bypasses including a switch.
Dependencies are inferred from the claim text.