Semiconductor device and information processing system including the same

A semiconductor device comprising:

• a semiconductor substrate;
• first and second bumps provided over the semiconductor substrate;
• first and second penetration electrodes each penetrating the semiconductor substrate;
• a first conductive structure making a first electrical path between the first bump and the first penetration electrode;
• and
• a second conductive structure making a second electrical path between the second bump and the second penetration electrode;
• the second conductive structure being smaller in resistance value than the first conductive structure.

A semiconductor device comprising:

• a first chip including first and second main surfaces opposed to each other, a first semiconductor substrate provided on aside of the first main surface, first and second bumps provided on the first main surface, third and fourth bumps provided on the second main surface, a first conductive structure which makes a first electrical path between the first and third bumps including a first penetration electrode which penetrates the first semiconductor substrate, and a second conductive structure which makes a second electrical path between the second and fourth bumps including a second penetration electrode which penetrates the first semiconductor substrate;
• and
• a second chip including third and fourth main surfaces opposed to each other, a second semiconductor substrate provided on a side of the third main surface, fifth and sixth bumps provided on the third main surface, seventh and eighth bumps provided on the fourth main surface, a third conductive structure which makes a third electrical path between the fifth and seventh bumps including a third penetration electrode which penetrates the second semiconductor substrate, and a fourth conductive structure which makes a fourth electrical path between the sixth and eighth bumps including a fourth penetration electrode which penetrates the second semiconductor substrate;
• the second chip being connected with the first chip such that the third and fourth bumps of the first chip are connected respectively with the fifth and sixth bumps of the second chip, and the second conductive structure of the first chip being smaller in resistance value than the first conductive structure of the first chip.