Semiconductor packages having passive elements mounted thereonto
AssigneeSamsung Electronics Co., Ltd.
InventorsHeung-kyu Kwon, Hyung-Jun Lim, Byeong-yeon Cho
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Abstract
A semiconductor package onto which a plurality of passive elements is mounted. A substrate includes a first surface and a second surface. A semiconductor chip is on one of the first surface and the second surface of the substrate. A plurality of passive elements are on the substrate. The plurality of passive elements include a plurality of first passive elements and a plurality of second passive elements that are taller than the plurality of first passive elements. The plurality of first passive elements are on at least one of the first surface and the second surface, and at least two of the plurality of second passive elements are on the second surface.
Claims11
A semiconductor package comprising:
- a substrate including a first surface and a second surface;
- a semiconductor chip on one of the first surface and the second surface of the substrate;
- and
- a plurality of passive elements on the substrate, the plurality of passive elements including,
- a plurality of first passive elements, and
- a plurality of second passive elements that are taller than the plurality of first passive elements, wherein
- the plurality of first passive elements are on at least one of the first surface and the second surface, and at least two one of the plurality of second passive elements is on the second surface.
A semiconductor package comprising:
- a substrate including a first surface and a second surface;
- a semiconductor chip on the first surface of the substrate;
- a plurality of passive elements on the substrate, the plurality of passive elements including,
- a plurality of first passive elements, and
- a plurality of second passive elements that are taller than the plurality of first passive elements, the plurality of first passive elements being on the second surface, and the plurality of second passive elements being on the first surface;
- an upper package on the second surface of the substrate;
- and
- a plurality of test terminals on the second surface of the substrate.
A semiconductor package comprising:
- a substrate including a first surface, a second surface and at least one opening;
- a semiconductor chip on the first surface of the substrate;
- a plurality of passive elements, the plurality of passive elements including,
- a plurality of first passive elements, and
- a plurality of second passive elements that are taller than the plurality of first passive elements;
- and
- an upper package on the first surface of the substrate, wherein
- the plurality of first passive elements are on at least one of the first surface and the second surface,
- at least one of the plurality of second passive elements is on a surface of the upper package facing the first surface of the substrate, the at least one second passive element on the upper package passing through the at least one opening, and
- the remaining second passive elements are on the second surface of the substrate.
Dependencies are inferred from the claim text.