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US 2011/0079923 A1Published application
Vertically Stackable Dies Having Chip Identifier Structures
AssigneeQUALCOMM Incorporated
InventorJungwon Suh
Life of this patent
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Abstract
A vertically stackable die having a chip identifier structure is disclosed. In a particular embodiment, a semiconductor device is disclosed that includes a die comprising a first through silicon via to communicate a chip identifier and other data. The semiconductor device also includes a chip identifier structure that comprises at least two through silicon vias that are each hard wired to an external electrical contact.
Claims41
A semiconductor device comprising:
- a die comprising a first through silicon via to communicate a chip identifier and other data;
- and
- a chip identifier structure that comprises at least two through silicon vias that are each hard wired to an external electrical contact.
A multi-die stacked semiconductor device comprising:
- a first die comprising a first chip identifier structure that comprises a number N of through silicon vias that are each hard wired to a first set of external electrical contacts, the number N comprising an integer greater than one;
- and
- a second die comprising a second chip identifier structure that comprises N through silicon vias that are each hard wired to a second set of electrical contacts.
A method of making a stacked multi-die semiconductor device, the method comprising:
- forming a stack of N dies, wherein each die comprises:
- a chip identifier structure that comprises a first set of N through silicon vias that are each hard wired to a set of external electrical contacts;
- chip identifier selection logic coupled to the chip identifier structure;
- and
- a chip select structure that comprises a second set of N through silicon vias coupled to the chip identifier selection logic, wherein N is an integer greater than one;
- and
- coupling each external electrical contact in each set of external electrical contacts to a voltage source or to ground, wherein each of the first set of N through silicon vias has a pad that is coupled to an adjacent through silicon via and each of the second set of N through silicon vias is coupled to its own respective pad.
4 more elements
A method comprising:
- a first step for forming a stack of N dies, wherein each die comprises:
- a chip identifier structure that comprises a first set of N through silicon vias that are each hard wired to a set of external electrical contacts;
- chip identifier selection logic coupled to the chip identifier structure;
- and
- a chip select structure that comprises a second set of N through silicon vias coupled to the chip identifier selection logic, wherein N is an integer greater than one;
- and
- a second step for coupling each external electrical contact in each set of external electrical contacts to a voltage source or to ground, wherein each of the first set of the N through silicon vias has a pad that is coupled to an adjacent through silicon via and each of the second set of the N through silicon vias is coupled to its own respective pad.
4 more elements
A method comprising:
- receiving design information representing at least one physical property of a semiconductor device, the semiconductor device comprising:
- a first die comprising a first chip identifier structure that comprises a number N of through silicon vias that are each hard wired to a first set of external electrical contacts, the number N comprising an integer greater than one;
- and
- a second die stacked above the first die, the second die comprising a second chip identifier structure that comprises N through silicon vias that are each hard wired to a second set of electrical contacts;
- transforming the design information to comply with a file format;
- and
- generating a data file comprising the transformed design information.
4 more elements
A method comprising:
- receiving a data file comprising design information corresponding to a semiconductor device;
- and
- fabricating the semiconductor device according to the design information, wherein the semiconductor device comprises:
- a first die comprising a first chip identifier structure that comprises a number N of through silicon vias that are each hard wired to a first set of external electrical contacts, the number N comprising an integer greater than one;
- and
- a second die stacked above the first die, the second die comprising a second chip identifier structure that comprises N through silicon vias that are each hard wired to a second set of electrical contacts.
3 more elements
A method comprising:
- receiving design information comprising physical positioning information of a packaged semiconductor device on a circuit board, the packaged semiconductor device comprising a semiconductor structure comprising:
- a first die comprising a first chip identifier structure that comprises a number N of through silicon vias that are each hard wired to a first set of external electrical contacts, the number N comprising an integer greater than one;
- and
- a second die stacked above the first die, the second die comprising a second chip identifier structure that comprises N through silicon vias that are each hard wired to a second set of electrical contacts;
- and
- transforming the design information to generate a data file.
3 more elements
A method comprising:
- receiving a data file comprising design information comprising physical positioning information of a packaged semiconductor device on a circuit board;
- and
- manufacturing the circuit board configured to receive the packaged semiconductor device according to the design information, wherein the packaged semiconductor device comprises a semiconductor structure comprising:
- a first die comprising a first chip identifier structure that comprises a number N of through silicon vias that are each hard wired to a first set of external electrical contacts, the number N comprising an integer greater than one;
- and
- a second die stacked above the first die, the second die comprising a second chip identifier structure that comprises N through silicon vias that are each hard wired to a second set of electrical contacts.
3 more elements
A multi-die stacked semiconductor device comprising:
- a first die comprising first means for identifying a chip that comprises a number N of through silicon vias that are each hard wired to a first set of means for making external electrical contact, the number N comprising an integer greater than one;
- and
- a second die comprising second means for identifying a chip that comprises N through silicon vias that are each hard wired to a second set of means for making electrical contact.
A computer-readable tangible medium storing instructions executable by a computer, the instructions comprising:
- instructions that are executable by the computer to initiate forming a stack of N dies, wherein each die comprises:
- a chip identifier structure that comprises a first set of N through silicon vias that are each hard wired to a set of external electrical contacts;
- chip identifier selection logic coupled to the chip identifier structure;
- and
- a chip select structure that comprises a second set of N through silicon vias coupled to the chip identifier selection logic, wherein N is an integer greater than one;
- and
- instructions that are executable by the computer to initiate coupling each external electrical contact in each set of external electrical contacts to a voltage source or to ground, wherein each of the first set of the N through silicon vias has a pad that is coupled to an adjacent through silicon via and each of the second set of the N through silicon vias is coupled to its own respective pad.
4 more elements
A method comprising:
- receiving a chip identifier signal based on a position of a first die within a die stack, wherein the chip identifier signal is received at the first die via multiple through silicon vias of the first die;
- and
- determining, based on the received chip identifier signal, whether the first die is a particular die that is indicated by a received chip selection signal.
Dependencies are inferred from the claim text.