Connection for Off-Chip Electrostatic Discharge Protection
AssigneeInterconnect Portfolio LLC
InventorPhil P. Marcoux
Life of this patent
Estimating the term…
Abstract
A method and apparatus for off-chip ESD protection, the apparatus includes an unprotected IC 22 stacked on an ESD protection chip 24 and employing combinations of edge wrap 32 and through-silicon via connectors 44 for electrical connection from an external connection lead 34 on a chip carrier 84 or system substrate 64, to an ESD protection circuit, and to an I/O trace 46 of the unprotected IC 22. In one embodiment the invention provides an ESD-protected stack 50 of unprotected IC chips 52, 54 that has reduced hazard of mechanical and ESD-damage in subsequent handling for assembly and packaging. The method includes a manufacturing method 170 for mass producing embedded edge wrap connectors 32, 38 during the chip manufacturing process.
Claims20
A semiconductor stack assembly having ESD protection comprising, a first semiconductor chip including an integrated circuit (IC) with an input/output (I/O) trace without on-chip electrostatic discharge (ESD) protection;
- and, a second chip having an ESD protection circuit, said first chip being electrically connected to said second chip with a conductor to said ESD protection circuit and said I/O trace wherein said conductor is formed during manufacture of said chips.
A method for making an embedded edge wrap conductor from a blank of material for use for production of multiple IC chips upon separation, comprising the steps of;
- forming holes through said blank overlapping the border between potential chips, and, placing a layer of insulating material on the interior surface of said hole in said blank, and, inserting a conducting material in said hole, and, singulating the chips by cutting through said border area and a portion of the conducting material resulting from said placing step.
A method for making an embedded edge wrap conductor from a blank of material for use for production of multiple IC chips upon separation comprising the steps of;
- masking the chip to create cove portions adjacent the area where the chips will be separated, and trenching the masked area to form sidewalls with coves in the masked areas, and, insulating said sidewalls and coves in said trench, and, removing insulation to open contact on said coves where contact is desired, and depositing conducting material in said trench and coves, and, singulating the chips along said trench.
A conductor for use with a chip having a sidewall, wherein said conductor is embedded in said sidewall and includes a first contact surface on the top surface of said conductor and a second contact surface on the bottom surface of said conductor.
Dependencies are inferred from the claim text.