Chip package and fabrication method thereof
AssigneeXintec Inc.
InventorChien-Hung LIU
Life of this patent
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Abstract
A chip package and a fabrication method thereof are provided. The chip package includes a semiconductor substrate containing a semiconductor component and a conductive pad thereon. A through hole penetrates the semiconductor substrate from a backside thereof to expose the conductive pad. A redistribution layer is below the backside of the semiconductor substrate and electrically connected to the conductive pad in the through hole. A conductive trace layer is below the redistribution layer and extended along a sidewall of the semiconductor substrate to electrically contact with an edge of the redistribution layer.
Claims23
A chip package, comprising:
- a semiconductor substrate, having a first surface and an opposite second surface, containing a semiconductor component and a conductive pad disposed on the first surface;
- a through hole extending from the second surface of the semiconductor substrate to the conductive pad;
- a redistribution layer disposed under the second surface of the semiconductor substrate, electrically connecting to the conductive pad in the through hole, wherein an edge of the redistribution layer is exposed at a sidewall of the semiconductor substrate;
- and
- a conductive trace layer disposed below the redistribution layer, extending to the sidewall of the semiconductor substrate to electrically contact with the redistribution layer.
A method for fabricating a chip package, comprising:
- providing a semiconductor wafer, having a first surface and an opposite second surface, wherein the semiconductor wafer contains a plurality of semiconductor components and a plurality of conductive pads disposed on the first surface;
- forming a plurality of through holes, extending from the second surface of the semiconductor wafer to the conductive pads;
- forming a redistribution layer under the second surface of the semiconductor wafer, electrically connecting to the conductive pads in the through holes, wherein an edge of the redistribution layer is exposed at a sidewall of the semiconductor wafer;
- and
- forming a conductive trace layer below the redistribution layer, extending to the sidewall of the semiconductor wafer to electrically contact with the redistribution layer.
Dependencies are inferred from the claim text.