Bump structure, chip package structure including the same and method of manufacturing the same
AssigneeIndustrial Technology Research Institute
InventorsSu Tsai LU, Yu Wei Huang
Life of this patent
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AssigneeIndustrial Technology Research Institute
InventorsSu Tsai LU, Yu Wei Huang
Estimating the term…
A bump structure includes a first substrate, a plurality of first bond pads, a plurality of dielectric bumps, a plurality of under bump metal layers, and a plurality of metal layers. The plurality of first bond pads are spaced apart on the first substrate. The plurality of dielectric bumps disposed corresponding to the first bond pads electrically isolate the first bond pads from each other. Each under bump metal layer is formed between the respective first bond pad and the dielectric bump, extending through a side surface of the respective dielectric bump, and correspondingly forming an extension portion between two adjacent dielectric bumps, wherein each extension portion has a length along the extending direction thereof shorter than the pitch between two adjacent dielectric bumps. Each metal layer is formed on the side surface of the respective dielectric bump and the respective extension portion.
A bump structure, comprising:
A bump structure, comprising:
A chip package structure, comprising:
A chip package structure, comprising:
A method of manufacturing a bump structure, comprising steps of:
A method of manufacturing a bump structure, comprising steps of:
A method of manufacturing a bump structure, comprising steps of:
Dependencies are inferred from the claim text.