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US 2011/0079884 A1Published application
Hydrogen Passivation of Integrated Circuits
AssigneeTexas Instruments Incorporated
InventorsGul B. Basim, Scott R. Summerfelt, Ted S. Moise
Life of this patent
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Abstract
An integrated circuit with a passivation trapping layer. An integrated circuit with a hydrogen or deuterium releasing layer underlying a passivation trapping layer. Method for forming an integrated circuit having a hydrogen or deuterium releasing layer. Method for forming an integrated circuit having a passivation trapping layer.
Claims20
An integrated circuit, comprising:
- a substrate;
- a transistor coupled to said substrate;
- a PMD layer coupled to said substrate;
- and
- a passivation trapping layer overlying said PMD layer.
2 more elements
An integrated circuit, comprising:
- a substrate;
- a transistor coupled to said substrate, where an interface between said substrate and a gate dielectric of said transistor is passivated;
- a passivation trapping layer overlying said transistor.
- a PMD layer overlying to said passivation trapping layer.
1 more element
A process of forming an integrated circuit, comprising:
- providing a partially processed integrated circuit having a transistor and a PMD layer overlying said transistor;
- passivating said partially processed integrated circuit;
- and
- after said passivating step, depositing a passivation trapping layer over said PMD layer.
1 more element
A process of forming an integrated circuit, comprising:
- providing a partially processed integrated circuit that includes a transistor;
- passivating said partially processed integrated circuit;
- after said passivating step, depositing a passivation trapping layer over said transistor;
- and
- forming a PMD layer over said passivation trapping layer.
2 more elements
Dependencies are inferred from the claim text.