Back to results
US 2011/0079847 A1Published application
Semiconductor Device
OwnerMika Ebihara, Tomomitsu Risakiinventors
Life of this patent
Estimating the term…
Abstract
Provided is a semiconductor device capable of easily setting a holding voltage with a low trigger voltage by locally forming a P-type diffusion layer between N-type source and drain diffusion layers of an NMOS transistor having a conventional drain structure used as an electrostatic protective element of the semiconductor device.
Claims8
-6. (canceled)
A semiconductor device comprising:
- a semiconductor substrate;
- a P-type well region disposed in the semiconductor substrate;
- a field oxide film disposed on the P-type well region and surrounding an active element region;
- a gate electrode disposed on a gate oxide film disposed on the active element region;
- N-type source and drain regions surrounded by the field oxide film and the gate electrode;
- and
- a P-type region disposed in contact with the N-type source region but not in contact with the N-type drain region for lowering a breakdown voltage of the semiconductor device.
4 more elements
Dependencies are inferred from the claim text.