Memory cell and manufacturing method thereof and memory structure

A method of manufacturing a memory cell, comprising:

• providing a substrate;
• forming an isolation layer over the substrate;
• forming a gate over the isolation layer;
• forming a charge storage structure over the gate and the isolation layer;
• forming a channel material layer over the charge storage structure;
• and
• forming first source/drain regions in the channel material layer at two sides of the gate and forming a second source/drain region in the channel material layer at top of the gate.

A memory structure, comprising:

• a substrate;
• and
• at least one memory array, disposed over the substrate, wherein the memory array comprises:
• an isolation layer, disposed over the substrate;
• two select lines, disposed over the isolation layer;
• a plurality of word lines, disposed over the isolation layer and located between the plurality of select lines;
• a charge storage structure, disposed over the isolation layer, the plurality of select lines, and the plurality of word lines;
• a plurality of first bit lines, disposed over the charge storage structure located at two sides of the plurality of select lines and between the plurality of word lines, respectively;
• a plurality of second bit lines, disposed over the charge storage structure located at top of the plurality of select lines and the plurality of word lines, respectively;
• and
• a plurality of channel layers, disposed over the charge storage structure located at sidewalls of the plurality of select lines and the plurality of word lines, respectively, and each of the plurality of channel layers electrically connecting with the corresponding first bit line and the corresponding second bit line.