US 2011/0079834 A1Published application

Semiconductor integrated circuit device

AssigneeRenesas Electronics Corporation

InventorsMasayuki YANAGISAWA, Hiroshi Furuta, Hiroyasu Kitajima, Katsuya Izumi

Life of this patent

Estimating the term…

Loading patent…

Abstract

A semiconductor integrated circuit device has: a MISFET having source/drain diffusion layers; first plugs respectively connected to the source/drain diffusion layers; a first interconnection connected to one of the source/drain diffusion layers through the first plug; a second plug electrically connected to the other Of the source/drain diffusion layers through the first plug; a second interconnection connected to the second plug; and a capacitor electrode located above a gate electrode of the MISFET. The first interconnection is formed not above the lower capacitor electrode, while the second interconnection is formed above the upper capacitor electrode. A plug connecting the first interconnection and another interconnection is not provided at an upper location of the one of the source/drain diffusion layers. The first interconnection is not provided at an upper location of the other of the source/drain diffusion layers.

Claims12

Dependent claims

A semiconductor integrated circuit device comprising:

a MISFET having a source diffusion layer and a drain diffusion layer;
first plugs connected to said source diffusion layer and said drain diffusion layer, respectively;
a first interconnection connected to one of said source diffusion layer and said drain diffusion layer through said first plug;
a second plug electrically connected to the other of said source diffusion layer and said drain diffusion layer through said first plug;
a second interconnection connected to said second plug;
and
a capacitor electrode or a data memory section at least a part of which is located above a gate electrode of said MISFET,
wherein said first interconnection is formed in an interconnect layer that is formed in a same process as or before a process of a lower electrode of said part of said capacitor electrode or said data memory section, and
said second interconnection is formed in an interconnect layer that is located above an upper electrode of said part of said capacitor or said data memory section,
wherein a plug connecting said first interconnection and another interconnection is not provided at an upper location of a region of said one of said source diffusion layer and said drain diffusion layer, and
an interconnection formed in a same process as that of said first interconnection is not provided at an upper location of a region of said other of said source diffusion layer and said drain diffusion layer.

8 more elements

A semiconductor integrated circuit device comprising:

a memory cell array region having a plurality of memory cells;
and
a logic circuit region,
wherein said memory cell array region comprises:
a MISFET for memory cell;
and
a part of a capacitor electrode or a data memory section that is provided above a gate electrode of said MISFET for memory cell and has an upper node and a lower node,
wherein said logic circuit region comprises:
a MISFET having a gate electrode, a source/drain diffusion layer and a drain/source diffusion layer;
a first lower layer plug electrically connected to said source/drain diffusion layer;
a second lower layer plug electrically connected to said drain/source diffusion layer;
an upper layer plug provided above said first lower layer plug and said second lower layer plug;
a first interconnection provided in an interconnect layer below said lower node;
and
a second interconnection provided in an interconnect layer above said upper node,
wherein said first interconnection is electrically connected to said source/drain diffusion layer through said first lower layer plug,
said second interconnection is electrically connected to said second lower layer plug through said upper layer plug,
said upper layer plug is not provided at an upper location of a region of said source/drain diffusion layer, and
said first interconnection is not provided at an upper location of a region of said drain/source diffusion layer.

16 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/896,233Filed 1 Oct 2010
Priority: JP 2009-2309312 Oct 2009
Published: 7 Apr 2011
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10B 53/40
Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors: characterised by the peripheral circuit region
H10B 12/0335
The capacitor extending over the transistor: making a connection between the transistor and the capacitor, e.g. plug
H10B 12/09
Manufacture or treatment: with simultaneous manufacture of the peripheral circuit region and memory cells
H10B 12/485
Data lines or contacts therefor: bit line contacts