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US 2011/0079823 A1Published application
Vertical transistor and array of vertical transistor
AssigneeNanya Technology Corporation
InventorsTieh-Chiang Wu, Yu-Teh Chiang
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Abstract
A vertical transistor includes a substrate, a gate, a source region, a drain region, a channel region and a gate dielectric layer. A trench is formed in the substrate, and the gate is disposed in the trench. The source region is disposed in the substrate beneath the gate. The drain region is disposed above the gate. The channel region is disposed at two sides of the gate and located between the source region and the drain region. The gate dielectric layer is located between the gate and the channel region.
Claims16
A vertical transistor, comprising:
- a substrate, having a trench;
- a gate, disposed in the trench;
- a source region, disposed in the substrate beneath the gate;
- a drain region, disposed above the gate;
- a channel region, disposed at two sides of the gate and located between the source region and the drain region;
- and
- a gate dielectric layer, located between the gate and the channel region.
4 more elements
An array of a vertical transistor, comprising:
- a substrate;
- a plurality of source regions, disposed in the substrate in parallel along a first direction;
- a plurality of gate lines, disposed in the substrate in parallel along a second direction and above the source regions;
- a plurality of isolation structures, disposed between the source regions and between the gate lines;
- a plurality of drain regions, disposed above the gate lines;
- a plurality of channel regions, wherein each channel region is disposed at two sides of each gate line and located between a corresponding source region and a corresponding drain region;
- and
- a plurality of gate dielectric layers, located between the gate lines and the channel regions.
5 more elements
Dependencies are inferred from the claim text.