Multi-chip module for battery power control

A method comprising:

• obtaining a leadframe structure comprising a first lead, a second lead, a third lead and a fourth lead;
• mounting an integrated circuit chip to the leadframe structure;
• mounting at least one semiconductor chip comprising a first power transistor and a second power transistor on the leadframe structure;
• attaching a first connection structure to the integrated circuit chip and to the first power transistor;
• attaching a second connection structure to the integrated circuit chip and to the second power transistor;
• attaching a third connection structure to the integrated circuit chip and to the third lead;
• attaching a fourth connection structure to the integrated circuit chip and to the fourth lead, the fourth lead being separate from the third lead;
• and
• molding a material around at least part of the integrated circuit chip, the first power transistor, the second power transistor, the first connection structure, and the second connection structure, thereby forming a multichip module,
• wherein the first lead provides an electrical connection to the first power transistor and the second lead provides an electrical connection to the second power transistor, and
• wherein the first and second leads are at a first end of the multi-chip module, and the third and fourth leads are at a second end of the multi-chip module.

A method comprising:

• obtaining a metal leadframe structure including a first lead, a second lead, a third lead, a fourth lead, and at least two independent die mounting pads electrically isolated from one another, the at least two independent die mounting pads including a first pad for mounting at least one integrated circuit chip and a second pad for mounting at least one transistor device chip;
• mounting the at least one integrated circuit chip to the first pad;
• mounting a first MOSFET transistor and a second MOSFET transistor on the second pad, the first MOSFET transistor having a gate electrode, a source electrode, and a drain electrode, the first MOSFET transistor being mounted so that its drain electrode faces the second pad and is electrically coupled to the second pad, the second MOSFET transistor having a gate electrode, a source electrode, and a drain electrode, the second MOSFET transistor being mounted so that its drain electrode faces the second pad and is electrically coupled to the second pad;
• attaching a first plurality of bonding wires that connect the integrated circuit chip to the first and second leads and to at least the gate electrodes of the first and second MOSFET transistors, the first plurality of bonding wires having a first diameter;
• and
• attaching a second plurality of bonding wires that connect the source electrodes of the first and second MOSFET transistors to the third and fourth leads, respectively, the second plurality of bonding wires having a second diameter that is greater than the first diameter.