Phase error detection apparatus, phase error detection method, and reproduction apparatus

A phase error detection method comprising the steps of:

• sampling an input signal digitally;
• calculating firstly a phase error using a first operation expression based on Ak−1+Ak, where Ak denotes the sampling value of said input signal after a zero cross and Ak−1 represents the sampling value of said input signal before the zero cross;
• calculating secondly the phase error using a second operation expression based on min(Ak, Ak−1), where min(x, y) constitutes an operator for selecting either x or y, which is the smaller of the two;
• and
• determining whether or not an absolute value |Ak−Ak−1| of the difference between the sampling value Ak of said input signal after the zero cross on the one hand, and the sampling value Ak−1 of said input signal before the zero cross on the other hand, is equal to or smaller than a predetermined first threshold value, said determining step further outputting selectively as phase error detection information either a calculated value from said first calculating step or a calculated value from said second calculating step depending on the result of the determination.

A reproduction apparatus comprising:

• a reproduced signal acquisition block configured to acquire a reproduced signal of bit information recorded on a recording medium;
• a sampling block configured to sample said reproduced signal digitally;
• a first phase error calculation block configured to calculate a phase error using a first operation expression based on Ak−1+Ak, where Ak denotes the sampling value of said reproduced signal after a zero cross and Ak−1 represents the sampling value of said reproduced signal before the zero cross;
• a second phase error calculation block configured to calculate the phase error using a second operation expression based on min(Ak, Ak−1), where min(x, y) constitutes an operator for selecting either x or y, which is the smaller of the two;
• a selective output block configured to determine whether or not an absolute value |Ak−Ak−1| of the difference between the sampling value Ak of said reproduced signal after the zero cross on the one hand, and the sampling value Ak−1 of said reproduced signal before the zero cross on the other hand, is equal to or smaller than a predetermined first threshold value, said selective output block further outputting selectively as phase error detection information either a calculated value from said first phase error calculation block or a calculated value from said second phase error calculation block depending on the result of the determination;
• and
• a clock generation block configured to generate a clock by performing phase locked loop control known as PLL based on said phase error detection information output by said selective output block.

A phase error detection apparatus comprising:

• sampling means for sampling an input signal digitally;
• first phase error calculation means for calculating a phase error using a first operation expression based on Ak−1+Ak, where Ak denotes the sampling value of said input signal after a zero cross and Ak−1 represents the sampling value of said input signal before the zero cross;
• second phase error calculation means for calculating the phase error using a second operation expression based on min(Ak, Ak−1), where min(x, y) constitutes an operator for selecting either x or y, which is the smaller of the two;
• and
• selective output means for determining whether or not an absolute value |Ak−Ak−1| of the difference between the sampling value Ak of said input signal after the zero cross on the one hand, and the sampling value Ak−1 of said input signal before the zero cross on the other hand, is equal to or smaller than a predetermined first threshold value, said selective output means further outputting selectively as phase error detection information either a calculated value from said first phase error calculation means or a calculated value from said second phase error calculation means depending on the result of the determination.

A reproduction apparatus comprising:

• reproduced signal acquisition means for acquiring a reproduced signal of bit information recorded on a recording medium;
• sampling means for sampling said reproduced signal digitally;
• first phase error calculation means for calculating a phase error using a first operation expression based on Ak−1+Ak, where Ak denotes the sampling value of said reproduced signal after a zero cross and Ak−1 represents the sampling value of said reproduced signal before the zero cross;
• second phase error calculation means for calculating the phase error using a second operation expression based on min(Ak, Ak−1), where min(x, y) constitutes an operator for selecting either x or y, which is the smaller of the two;
• selective output means for determining whether or not an absolute value |Ak−Ak−1| of the difference between the sampling value Ak of said reproduced signal after the zero cross on the one hand, and the sampling value Ak−1 of said reproduced signal before the zero cross on the other hand, is equal to or smaller than a predetermined first threshold value, said selective output means further outputting selectively as phase error detection information either a calculated value from said first phase error calculation means or a calculated value from said second phase error calculation means depending on the result of the determination;
• and
• clock generation means for generating a clock by performing phase locked loop control known as PLL based on said phase error detection information output by said selective output means.