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US 2011/0049723 A1Published application
Methods and structures for controlling wafer curvature
AssigneeInternational Business Machines Corporation
InventorsMohammed Fazil Fayaz, Jeffery Burton Maxson, Anthony Kendall Stamper, Daniel Scott Vanslette
Life of this patent
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Abstract
Methods and structures for controlling wafer curvature during fabrication of integrated circuits caused by stressed films. The methods include controlling the conductor density of wiring levels, adding compensating stressed film layers and disturbing the continuity of stress films with the immediately lower layer. The structure includes integrated circuits having compensating stressed film layers.
Claims21
A method, comprising:
- selecting a wiring level design of an integrated circuit design, said design defining a physical wiring level of an integrated circuit chip on a wafer, wherein wires of said wiring level are formed of an electrical conductor in internal tensile stress and an interlevel dielectric layer of said wiring level is in internal tensile stress;
- determining if an electrical conductor shape density of said wiring level design is within a pre-defined range;
- if said shape density is below a lower limit of said range, increasing said shape density or if said shape density is greater than an upper limit of said range, decreasing said shape density;
- and
- fabricating said one or more of said integrated circuit chips on said wafer using wiring level design.
2 more elements
A method, comprising:
- forming multiple wiring levels on a wafer from a first wiring level nearest said wafer to a last wiring level, each wiring level of said of multiple wiring levels comprising respective damascene wires in a respective interlevel dielectric layer;
- forming a dielectric passivation layer on said last wiring level of said multiple wiring levels and a polyimide layer on said passivation layer, said polyimide layer in internal tensile stress;
- and
- wherein at least one compensating dielectric layer formed above said first wiring level is in internal compressive stress.
1 more element
A structure, comprising:
- multiple wiring levels on a wafer from a first wiring level nearest said wafer to a last wiring level, each wiring level of said of multiple wiring levels comprising respective damascene wires in a respective interlevel dielectric layer;
- a dielectric passivation layer on said last wiring level of said multiple wiring levels and a polyimide layer on said passivation layer, said polyimide layer in internal tensile stress;
- and
- at least one compensating dielectric layer formed above said first wiring level, said one or more compensating dielectric layers in internal compressive stress.
1 more element
A method, comprising:
- forming multiple wiring levels on a wafer from a first wiring level nearest said wafer to a last wiring level, each wiring level of said of multiple wiring levels comprising damascene wires in an interlevel dielectric layer;
- forming a terminal dielectric layer on said last wiring level of said multiple wiring levels;
- forming terminal pads on said terminal dielectric layer;
- forming a dielectric passivation layer on said terminal dielectric layer;
- forming a polyimide layer on said passivation layer, said polyimide layer internally in tensile stress;
- and
- forming vias and trenches in said polyimide layer, said terminal pads exposed in bottoms of said vias, said passivation layer but not said terminal pads exposed in bottoms of said trenches.
4 more elements
Dependencies are inferred from the claim text.