System and method for on-chip-variation analysis
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsLee-Chung Lu, Chung-Hsing Wang, Yuan-Te Hou
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Abstract
Apparatus is provided for performing timing analysis on a circuit. A first storage device portion stores a state dependent stage weight for each of a rising time arc and a falling time arc of each of a plurality of cells in a cell library. An adder is provided for calculating a sum of the state dependent stage weights for each of the cells that are included in a circuit path. A second storage device portion stores a table containing on chip variation (OCV) derating factors. The table is indexed by values of the sum. A total path delay is calculated for the circuit path, based on the OCV derating factor corresponding to the sum of the state dependent stage weights for the cells in the circuit path.
Claims20
Apparatus for performing timing analysis on a circuit, comprising:
- a first storage device portion storing a state dependent stage weight for each of a rising time arc and a falling time arc of each of a plurality of cells in a cell library;
- an adder for calculating a sum of the state dependent stage weights for each of the cells that are included in a circuit path;
- a second storage device portion that stores a table containing on chip variation (OCV) derating factors, the table being indexed by values of the sum;
- and
- means for calculating a total path delay for the circuit path, based on the OCV derating factor corresponding to the sum of the state dependent stage weights for the cells in the circuit path.
A computer readable storage medium encoded with computer program code, such that when the computer program code is executed by a processor, the processor performs a method, comprising the steps of:
- calculating a state dependent stage weight for each of a rising time arc and a falling time arc of each of a plurality of cells in a cell library;
- calculating a sum of the state dependent stage weights for each of the cells that are included in a circuit path;
- retrieving, from a table containing on chip variation (OCV) derating factors, an OCV derating factor corresponding to the sum of the state dependent stage weights for the cells in the circuit path, wherein the table is indexed by values of the sum of the state dependent stage weights;
- and
- calculating a total path delay for the circuit path, based on the retrieved OCV derating factor.
A method, comprising the steps of:
- (a) providing a storage device storing a state dependent stage weight for each of a rising time arc and a falling time arc of a each of a plurality of cells in a cell library;
- (b) calculating a sum of the state dependent stage weights for each of the cells that are included in a circuit path;
- (c) retrieving, from a table containing on chip variation (OCV) derating factors, an OCV derating factor corresponding to the sum of the state dependent stage weights for the cells in the circuit path, wherein the table is indexed by values of the sum of the state dependent stage weights;
- (d) calculating a total path delay for the circuit path, based on the retrieved OCV derating factor;
- (e) determining a design of the circuit path that satisfies timing requirements, based on the calculated total path delay;
- and
- (f) performing a tapeout of the design to form a computer readable storage medium encoded with data usable for controlling a semiconductor process to fabricate an integrated circuit containing the circuit path.
Dependencies are inferred from the claim text.