Method and System for Repartitioning a Hierarchical Circuit Design

A method for repartitioning a multilevel hierarchical description of a design unit comprising a plurality of macros, said method comprising the steps of

• identifying all macros containing latches,
• stripping each of these macros of all combinatorial logic and wiring located between the latches and primary inputs and outputs of said macro, thus generating latch macros, and
• based on unit connectivity, regrouping the stripped-off combinatorial logic and wiring, potentially including additional combinatorial logic into combinatorial macros.

A data processing system for execution of a data processing program comprising software code portions for repartitioning a multilevel hierarchical description of an electronic design unit comprising a plurality of macros into a set of combinatorial macros and a set of latch macros such that

• each combinatorial macro contains only combinatorial logic, and
• each latch macro contains one or several latches, each primary input and output of said latch macro coinciding with an input or an output of a latch within said latch macro.

A data processing system for generating and verifying timing assertions for an electronic design unit, comprising

• a repartition system for generating a repartitioned design unit in terms of latch macros and combinatorial macros and
• a timing system for generating timing assertions on the repartitioned design unit.

A data processing repartitioning system for repartitioning a multilevel hierarchical description of an electronic design unit with a plurality of macros, comprising

• a dissecting system for dissecting all macros into latch macros and signal cones and
• a merging system for creating combinatorial macros by merging signal cones along signal paths.

A program product comprising a computer useable medium including a computer readable program, wherein the computer readable program when executed on a computer causes the computer to

• generate a multilevel hierarchical description of an electronic design unit in terms of macros,
• repartition said design unit in terms of latch macros and combinatorial macros and
• generate timing assertions on the repartitioned design unit.

A program product comprising a computer useable medium including a computer readable program, wherein the computer readable program when executed on a computer causes the computer to

• dissect all macros of a hierarchical structure of an electronic circuit design unit into latch macros and signal cones and
• create combinatorial macros by merging signal cones along unit signal paths.