US 2011/0035644 A1Published application

Data Path Read/Write Sequencing for Reduced Power Consumption

AssigneeTexas Instruments Incorporated

InventorSudhir K. Madan

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Abstract

A solid-state memory such as a ferroelectric random access memory (FeRAM) with multiplexed internal data bus and reduced power consumption on data transfer. The memory stores data in the form of multi-byte data words with error correction coding (ECC). In a page mode read/write operation, data states stored in memory cells of the selected row are sensed by sense amplifiers arranged in first and second banks, which are associated with first and second groups of columns. The first bank of sense amplifiers, associated with the first group of columns and containing the ECC value, are coupled to to the internal bus, followed by coupling the second bank of sense amplifiers associated with the second group of columns to the internal bus. The internal bus is then placed in tri-state, following which the internal data bus is driven with data to be written into the second group of columns in that same row, that data latched into the second bank of sense amplifiers. The internal bus is then driven with the data to be written to the first group of columns in the row, and latched into the first bank of sense amplifiers. To the extent that the data in the second group of columns does not change from the read to write operations, power consumption otherwise necessary for switching the internal bus is avoided.

Claims32

Dependent claims

A solid-state memory device, comprising:

at least one memory array block including a plurality of memory cells arranged in rows and columns;
a first sense circuitry bank associated with a first group of columns of the at least one memory array block;
a second sense circuitry bank associated with a second group of columns of the at least one memory array block;
an internal data bus of a bit width corresponding to a number of columns in one of the groups of columns;
input/output circuitry coupled to the internal data bus, for arranging the contents of the first and second groups of columns sensed by the first and second sense circuitry banks into a data word comprised of a payload portion and an error correction coding (ECC) portion including an ECC value based on the contents of the payload portion, and for receiving input data corresponding to at least a portion of the data word;
error correction coding (ECC) logic for generating ECC values based on the contents of the payload portion of data words;
and
control logic, for controlling the input/output circuitry, ECC logic, and the first and second sense circuitry banks to perform a read/write sequence of a data word in a selected row of the at least one memory array block according to a plurality of operations comprising:
receiving input data to be stored;
enabling the first and second sense circuitry banks to sense data states stored in memory cells of the first and second group of columns, respectively, in a selected row of the at least one memory array block;
coupling the sensed data states from the first sense circuitry bank to the input/output circuitry via the internal data bus;
then coupling the sensed data states from the second sense circuitry bank to the input/output circuitry via the internal data bus;
generating the ECC value for a data word to be stored in the selected row, the data word including the received input data and the generated ECC value;
then coupling, to the internal data bus, a portion of the data word to be stored in memory cells of the second group of columns in the selected row;
and
then coupling, to the internal data bus, a portion of the data word to be stored in memory cells of the first group of columns in the selected row.

13 more elements

A method of performing a read and write access to a solid-state memory, the memory comprising at least one memory array block including a plurality of memory cells arranged in rows and columns, the method comprising the steps of:

sensing stored data states of memory cells in first and second groups of columns in a selected row of a memory array block, the stored data states constituting a data word comprising a payload portion and an error correction coding (ECC) portion for an ECC value based on the payload portion;
receiving input data to be written to at least a portion of an instance of the data word;
communicating the stored data states from the first group of columns to an internal data bus;
after the step of communicating the stored data states from the first group of columns, then communicating the stored data states from the second group of columns to the internal data bus;
generating an ECC value for the instance of the data word including the received input data;
after the steps of communicating the stored data states from the second group of columns and of generating the ECC value, then applying, to the internal data bus, data states to be written to memory cells in the second group of columns in the selected row of the memory array block;
and
then applying, to the internal data bus, data states to be written to memory cells in the first group of columns in the selected row of the memory array block.

5 more elements

Dependencies are inferred from the claim text.