Timing Failure Debug

A method of debugging a circuit, comprising.

• identifying a target signal in a circuit that may propagate a fault;
• generating transition delay test patterns to propagate the fault along the target signal;
• applying the transition delay test patterns to the target signal;
• monitoring devices along a path of the target signal to identify a physical location of the fault;
• identifying side signals for devices in fan-out branches of a net along the path of the target signal;
• and
• applying constraint values to the side signals so that the side signal so that a transition on the test signal created by a transition delay test pattern is propagated to outputs of the devices in the fan-out branches.

A method of timing failure debug, comprising:

• selecting a target signal region in a circuit where a timing-related defect may exist and a propagation path that passes through the target signal region to an observation point where a timing failure caused by the timing-related defect can be observed;
• generating, under one or more constraints, a test pattern that can activate the timing-related defect and propagate the timing failure along the propagation path, the one or more constraints including a first constraint that some or all side inputs along the propagation path are set to non-controlling values;
• applying the test pattern to the circuit;
• and
• monitoring the circuit along the propagation path using a transition signal measurement technique.