Out-of-order x86 microprocessor with fast shift-by-zero handling

A method for executing instructions in out-of-order execution microprocessor, the method comprising:

• generating a first indicator that indicates whether an instruction is dependent upon a condition code result of a shift instruction;
• executing the shift instruction and generating a second indicator that indicates whether a shift amount of the shift instruction is zero;
• and
• receiving the first and second indicators and generating a replay signal to cause the instruction to be replayed if the first indicator indicates the instruction is dependent upon the condition code result of the shift instruction and a second indicator indicates the shift amount of the shift instruction is zero.

A computer program product for use with a computing device, the computer program product comprising:

• a computer usable storage medium, having computer readable program code embodied in said medium, for specifying an out-of-order execution microprocessor, the computer readable program code comprising:
• first program code for specifying a register alias table, configured to generate a first indicator that indicates whether an instruction is dependent upon a condition code result of a shift instruction;
• second program code for specifying a first execution unit, configured to execute the shift instruction and to generate a second indicator that indicates whether a shift amount of the shift instruction is zero;
• and
• third program code for specifying a second execution unit, configured to receive the first and second indicators and to generate a replay signal to cause the instruction to be replayed if the first indicator indicates the instruction is dependent upon the condition code result of the shift instruction and a second indicator indicates the shift amount of the shift instruction is zero.