US 2011/0035571 A1 · ON-CHIP PACKET INTERFACE PROCESSOR ENCAPSULATING MEMORY ACCESS FROM MAIN PROCESSOR TO EXTERNAL SYSTEM MEMORY IN SERIAL PACKET SWITCHED PROTOCOL

Abstract

A computing and communication chip architecture is provided wherein the interfaces of processor access to the memory chips are implemented as a high-speed packet switched serial interface as part of each chip. In one embodiment, the interface is accomplished through a gigabit Ethernet interface provided by protocol processor integrated as part of the chip. The protocol processor encapsulates the memory address and control information like Read, Write, number of successive bytes etc, as an Ethernet packet for communication among the processor and memory chips that are located on the same motherboard, or even on different circuit cards. In one embodiment, the communication over head of the Ethernet protocol is further reduced by using an enhanced Ethernet protocol with shortened data frames within a constrained neighborhood, and/or by utilizing a bit stream switch where direct connection paths can be established between elements that comprise the computing or communication architecture.

Claims18

Dependent claims

An apparatus implementing a computing and communication chip architecture for integrated circuitry, comprising:

at least one memory device;
and
at least one packet processor uniquely associated with each of the at least one memory device, and
the at least one packet processor adapted to provide high speed packet switched serial interface for read and write access to the at least one memory device by encapsulating and decapsulating address, data and control information, using a packetized protocol for switched serial communication, and
further the at least one packet processor adapted to translate between multiple serialized protocols communicated over the high-speed packet switched serial interface,
wherein the at least one memory device and the at least one packet processor are co-located on a semiconductor die package having at least one external port over which the high-speed packet switched serial interface is accessible,
such that the high-speed packet switched serial interface transfers the serialized protocol packet, to an external device configured for read and write access to the at least one memory device using a serial packetized protocol.

4 more elements

A computer readable media having recorded thereon instructions for implementing a computing and communication chip architecture for integrated circuitry on a semiconductor die package, comprising:

instructions defining at least one memory device co-located on the semiconductor die package with at least one packet processor uniquely associated with each of the at least one memory device, the at least one packet processor adapted to provide a high-speed packet switched serial interface for memory access to the at least memory device by encapsulating and decapsulating address data and control information using a packetized protocol for switched serial communication;
and
further instructions defining the at least one packet processor adapted to translate between multiple serialized protocols communicated over the high-speed packet switched serial interface, and
instructions defining at least one external port to the semiconductor die package over which the high-speed packet switched serial interface is accessible,
such that the high-speed packet switched serial interface transfers the serialized protocol packet to an external device configured for read and write access to the at least one memory device using a serial packetized protocol.

2 more elements

Dependencies are inferred from the claim text.

On-chip packet interface processor encapsulating memory access from main processor to external system memory in serial packet switched protocol

Life of this patent

On-chip packet interface processor encapsulating memory access from main processor to external system memory in serial packet switched protocol

Life of this patent

Abstract

Claims18