Microprocessor with alu integrated into store unit

A method for a superscalar pipelined microprocessor to process an instruction, the microprocessor having a register set defined by an instruction set architecture of the microprocessor, a cache memory, execution units, and a store unit distinct from the other execution units of the microprocessor, the method comprising:

• receiving an instruction that specifies a source register of the register set and an operation to be performed on a source operand to generate a result, wherein said receiving the instruction is performed by the store unit;
• reading the source operand from the source register, wherein said reading the source operand is performed by the store unit;
• performing the operation on the source operand to generate the result, wherein said performing the operation is performed by an arithmetic/logic unit (ALU) of the store unit rather than forwarding the source operand to any of the other execution units of the microprocessor to perform the operation on the source operand to generate the result;
• operatively writing the result to the cache memory, wherein said operatively writing the result is performed by the store unit.

A computer program product for use with a computing device, the computer program product comprising:

• a computer usable storage medium, having computer readable program code embodied in said medium, for specifying a superscalar pipelined microprocessor, the computer readable program code comprising:
• first program code for specifying a register set, defined by an instruction set architecture of the microprocessor;
• second program code for specifying a cache memory;
• third program code for specifying execution units;
• and
• fourth program code for specifying a store unit, coupled to the cache memory, wherein the store unit is distinct from the other execution units of the microprocessor, the store unit comprising an arithmetic/logic unit (ALU);
• wherein the store unit is configured to receive an instruction that specifies a source register of the register set and an operation to be performed on a source operand to generate a result;
• wherein the store unit is configured to read the source operand from the source register;
• wherein the ALU is configured to perform the operation on the source operand to generate the result, rather than forwarding the source operand to any of the other execution units of the microprocessor to perform the operation on the source operand to generate the result;
• wherein the store unit is further configured to operatively write the result to the cache memory.