Microprocessor with alu integrated into load unit

A method for a superscalar pipelined microprocessor to process an instruction, the microprocessor having a register set defined by an instruction set architecture of the microprocessor, a cache memory, execution units, and a load unit distinct from the other execution units of the microprocessor, the method comprising:

• receiving an instruction that specifies a memory address of a source operand, an operation to be performed on the source operand to generate a result, and a destination register of the register set to which the result is to be stored wherein said receiving the instruction is performed by the load unit;
• reading the source operand from the cache memory, wherein said reading the source operand is performed by the load unit;
• performing the operation on the source operand to generate the result, wherein said performing the operation is performed by an arithmetic/logic unit (ALU) of the load unit rather than forwarding the source operand to any of the other execution units of the microprocessor to perform the operation on the source operand to generate the result;
• and
• outputting the result for subsequent retirement to the destination register, wherein said outputting the result is performed by the load unit.

A computer program product for use with a computing device, the computer program product comprising:

• a computer usable storage medium, having computer readable program code embodied in said medium, for specifying a superscalar pipelined microprocessor, the computer readable program code comprising:
• first program code for specifying a register set, defined by an instruction set architecture of the microprocessor;
• second program code for specifying a cache memory;
• third program code for specifying execution units;
• and
• fourth program code for specifying a load unit, coupled to the cache memory, wherein the load unit is distinct from the other execution units of the microprocessor, the load unit comprising an arithmetic/logic unit (ALU);
• wherein the load unit is configured to receive an instruction that specifies a memory address of a source operand, an operation to be performed on the source operand to generate a result, and a destination register of the register set to which the result is to be stored;
• wherein the load unit is configured to read the source operand from the cache memory;
• wherein the ALU is configured to perform the operation on the source operand to generate the result, rather than forwarding the source operand to any of the other execution units of the microprocessor to perform the operation on the source operand to generate the result;
• wherein the load unit is further configured to output the result for subsequent retirement to the destination register.