Actual instruction and actual-fault instructions for processing vectors

A method for processing faults in a processor, comprising:

• receiving an input vector that includes N elements;
• optionally receiving a predicate vector that includes N elements;
• determining when a fault is to be generated because a fault was masked during a prior operation, by, for each bit position of a fault-status register, determining that:
• the bit position of the fault-status register contains a predetermined value,
• one or more relevant elements of the input vector are active, and
• when the predicate vector is received, if one or more relevant elements of the predicate vector are active;
• and
• responsive to determining that the fault should be generated, generating a corresponding fault.

A processor that processes faults, comprising:

• an execution unit, wherein the execution unit is configured to:
• optionally receive a predicate vector that includes N elements;
• and
• generate a result vector, wherein when generating the result vector, if the predicate vector is received, for each element in the result vector for which a corresponding element of the predicate vector is active, otherwise, for each element of the result vector, the execution unit is configured to:
• determine element positions for which a fault was masked during a prior operation;
• and
• update elements in the result vector to identify a leftmost element for which a fault was masked.

A processor that processes faults, comprising:

• an execution unit, wherein the execution unit is configured to:
• receive an input vector that includes N elements;
• optionally receive a predicate vector that includes N elements;
• determine when a fault is to be generated because a fault was masked during a prior operation, by, for each bit position of a fault-status register, determining that:
• the bit position of the fault-status register contains a predetermined value,
• one or more relevant elements of the input vector are active, and
• when the predicate vector is received, if one or more relevant elements of the predicate vector are active;
• and
• responsive to determining that the fault should be generated, generating a corresponding fault.

A computer system that processes faults, comprising:

• a processor;
• a memory coupled to the processor, wherein the memory stores instructions and data for the processor;
• and
• an execution unit, wherein the execution unit is configured to:
• optionally receive a predicate vector that includes N elements;
• generate a result vector, wherein when generating the result vector, if the predicate vector is received, for each element in the result vector for which a corresponding element of the predicate vector is active, otherwise, for each element of the result vector, the execution unit is configured to:
• determine element positions for which a fault was masked during a prior operation;
• and
• update elements in the result vector to identify a leftmost element for which a fault was masked.

A computer system that processes faults, comprising:

• an execution unit, wherein the execution unit is configured to:
• receive an input vector that includes N elements;
• optionally receive a predicate vector that includes N elements;
• determine when a fault is to be generated because a fault was masked during a prior operation, by, for each bit position of a fault-status register, determining that:
• the bit position of the fault-status register contains a predetermined value,
• one or more relevant elements of the input vector are active, and
• when the predicate vector is received, if one or more relevant elements of the predicate vector are active;
• and
• responsive to determining that the fault should be generated, generating a corresponding fault.