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US 2011/0035564 A1Published application
Technique to perform memory disambiguation
AssigneeIntel Corporation
InventorsEvgeni Krimer, Guillermo Savransky, Idan Mondjak, Jacob Doweck
Life of this patent
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Abstract
A memory access management technique. More particularly, at least one embodiment of the invention relates to a technique to issue loads to a memory ahead of older store operations corresponding to the same target address.
Claims7
A processor comprising:
- a first logic to predict a load operation will not conflict with older pending store operations if a saturation counter circuit corresponding to the load operation is at least at a threshold value and a maximum rate of mispredictions has not occurred, wherein the saturation counter circuit is to be incremented if the load operation does not conflict with the older pending store operations;
- a watchdog flush counter circuit to be decremented if the prediction is not correct;
- and
- a watchdog disambiguation counter circuit to be incremented if the prediction was correct, wherein the first logic is to be disabled if the ratio of the disambiguation counter circuit value and the flush counter circuit value reaches a minimum value.
1 more element
A system comprising:
- a first memory to store a store instruction to store data to a first memory location and a load instruction to load data from the memory location;
- a processor to fetch the store instruction from the first memory before the load instruction,
- wherein a first logic to predict a load operation to not conflict with older pending store operations if a saturation counter circuit corresponding to the load operation is at least at a threshold value and a maximum rate of mispredictions has not occurred,
- wherein the saturation counter circuit increments if the load operation does not conflict with the older pending store operations,
- wherein a watchdog flush counter circuit decrements if the prediction is not correct;
- wherein a watchdog disambiguation counter circuit increments if the prediction was correct;
- and
- wherein the first logic disables the prediction if the ratio of the disambiguation counter circuit value and the flush counter circuit value reaches a minimum value.
5 more elements
Dependencies are inferred from the claim text.