Memory Controller with Loopback Test Interface

A single integrated circuit comprising:

• an interconnect integrated into the single integrated circuit;
• a processor coupled to the interconnect, wherein the processor is integrated into the single integrated circuit;
• and
• a memory controller coupled to the interconnect, wherein the memory controller is integrated into the single integrated circuit, and wherein the memory controller is programmable by the processor into a loopback test mode of operation, and wherein, in the loopback test mode, the memory controller is configured to receive a first write operation from the processor over the interconnect, and wherein the memory controller is configured to route write data from the first write operation through a plurality of drivers and receivers connected to a plurality of data pins that are capable of connection to one or more memory modules external to the integrated circuit, wherein the plurality of drivers and the plurality of receivers are integrated into the single integrated circuit, and wherein the memory controller is configured to capture the write data from the plurality of receivers into a buffer, and wherein the memory controller is configured to return the write data from the buffer as read data on the interconnect for a first read operation received from the processor on the interconnect.

A memory controller configured to couple to an interconnect to receive memory operations from one or more memory operation sources and further configured to couple to a memory interface to communicate with one or more memory modules, the memory controller comprising:

• a write data buffer;
• a second buffer;
• a read data buffer;
• a plurality of data drivers configured to drive data on a plurality of pins forming a data portion of the memory interface;
• a plurality of data receivers coupled to receive data on the plurality of pins;
• wherein the plurality of data drivers and the plurality of data receivers are coupled to the write data buffer, the read data buffer, and the second buffer;
• and
• a controller configured, in a loopback mode of operation, to respond to a write operation received on the interconnect by writing write data corresponding to the write operation into the write data buffer, driving the write data from the write data buffer through the plurality of data drivers and the plurality of data receivers, and capturing the write data from the plurality of data receivers into the second buffer;
• and wherein the controller is configured to respond to a read operation received on the interconnect in a loopback mode of operation by reading the write data from the second buffer, driving the write data through the plurality of data drivers and the plurality of data receivers, and capturing the write data in the read data buffer, and providing the write data from the read data buffer on the interconnect as read data for the read operation.