Microprocessor with repeat prefetch indirect instruction

A method for prefetching data into a microprocessor, the method comprising:

• decoding a repeat prefetch indirect instruction;
• and
• prefetching cache lines into the microprocessor in response to said decoding the repeat prefetch indirect instruction and as instructed by the repeat prefetch indirect instruction;
• wherein the repeat prefetch indirect instruction comprises:
• address operands used to calculate an address of a first entry in a prefetch table having a plurality of entries, wherein each entry of the prefetch table includes a prefetch address;
• and
• a count specifying the number of the cache lines to be prefetched into the microprocessor, wherein the memory address of each of the cache lines is specified by the prefetch address in one of the plurality of entries in the prefetch table.

A microprocessor in a system with a system memory, the microprocessor comprising:

• an instruction decoder, configured to decode a prefetch instruction that specifies a count of cache lines to prefetch from the system memory and an address that points to a table that holds memory addresses of the cache lines to prefetch;
• a count register, configured to store a remaining count of the cache lines to be prefetched, wherein the count register is initially loaded with the count specified in the prefetch instruction;
• and
• control logic, coupled to the instruction decoder and to the count register, the control logic configured to control the microprocessor to fetch the memory addresses of the cache lines from the table into the microprocessor and to prefetch the cache lines from the system memory into a cache memory of the microprocessor using the count register and the memory addresses fetched from the table.

A method for prefetching data into a microprocessor in a system with a system memory, the method comprising:

• decoding a prefetch instruction that specifies a count of cache lines to prefetch from the system memory and an address that points to a table that holds memory addresses of the cache lines to prefetch;
• maintaining a remaining count of the cache lines to be prefetched, wherein the remaining count is initially the count specified in the prefetch instruction;
• and
• prefetching the cache lines from the system memory into a cache memory of the microprocessor using the remaining count and the memory addresses from the table.