Storage device, and memory controller

A storage device comprising a semiconductor memory, and a memory controller for controlling the semiconductor memory, wherein

• the semiconductor memory has a plurality of physical pages,
• the physical page has a data section and a management section,
• the data section stores data having a specific logical address, and the management section stores management data,
• the memory controller comprises a scramble pattern generator for generating a scramble pattern, a scramble processor for scrambling by using the scramble pattern generated by the scramble pattern generator, a logical and physical address conversion table for storing a correspondence between the logical address and the physical address which is an address of a physical page of the semiconductor memory, and a controller for controlling the scramble pattern generator and the scramble processor,
• for the data section, the controller controls the scramble pattern generator to generate a scramble pattern on the basis of a logical address specific to the data section, and controls the scramble processor to scramble the data of the data section corresponding to the logical address by using the scramble pattern, and
• for the management section, the controller controls the scramble pattern generator to generate a scramble pattern on the basis of a physical address as the write destination of the management section, and controls the scramble processor to scramble the management data by using the scramble pattern, so that data is written and read to and from the semiconductor memory.

A memory controller for writing and reading in a semiconductor memory having a plurality of physical pages, comprising:

• a scramble pattern generator for generating a scramble pattern, a scramble processor for scrambling by using the scramble pattern generated by the scramble pattern generator, a logical and physical address conversion table for storing a correspondence between the logical address and the physical address which is an address of a physical page of the semiconductor memory, and a controller for controlling the scramble pattern generator and the scramble processor, wherein
• the physical page is managed by dividing to a data section and a management section,
• the data section stores data having a specific logical address, and the management section stores management data, and
• for the data section, the controller controls the scramble pattern generator to generate a scramble pattern on the basis of a logical address specific to the data section, and controls the scramble processor to scramble the data of the data section corresponding to the logical address by using the scramble pattern, and
• for the management section, the controller controls the scramble pattern generator to generate a scramble pattern on the basis of a physical address as the write destination of the management section, and controls the scramble processor to scramble the management data by using the scramble pattern, so that data is written and read to and from the semiconductor memory.