US 2011/0035531 A1Published application

Coherency control system, coherency control apparatus and coherency control method

AssigneeNEC Corporation

InventorKOUJI KOBAYASHI

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Abstract

A coherency control system includes a logical-physical address translation unit which translates a logical address including a first tag and an index address into a physical address including a second tag and the index address, a request output unit which transmits a load request, a corresponding state storage unit which stores a relation state between an area of the second storage apparatus and an area of the first storage apparatus based on the way number included in the load request and the second tag and the index address of the physical address also included in the load request which has been received, and an invalidation instructing unit which transmits an invalidation instruction including the index address and the way number based on the second tag of the physical address included in the store request and the relation state stored in the corresponding state storage unit.

Claims13

Dependent claims

A coherency control system, comprising:

a logical-physical address translation unit which translates a logical address including a first tag, an index address and an offset address of a first storage unit of a set associative system into a physical address of a second storage unit, the physical address including a second tag, the index address and the offset address;
a request output unit which transmits a load request including at least the physical address and a way number of a way to which an area of the first storage unit designated by the logical address corresponding to said physical address belongs;
a corresponding state storage unit which stores a relation state between an area of the second storage unit and an area of the first storage unit based on the way number included in the load request which has been received and the second tag and the index address of the physical address also included in the load request which has been received;
and
an invalidation instructing unit which receives a store request including the physical address, and transmits an invalidation instruction including the index address and the way number based on the second tag of the physical address included in the store request which has been received and the relation state stored in the corresponding state storage unit.

2 more elements

A coherency control apparatus, comprising:

a corresponding state storage unit which stores, based on a received load request including a physical address of a second storage unit which is translated from a logical address including a first tag, an index address and an offset address of a first storage unit of a set associative system and which includes a second tag, the index address and the offset address, and a way number of a way to which an area of the first storage unit designated by the logical address corresponding to said physical address belongs, a relation state between an area of the second storage unit and an area of the first storage unit based on the way number included in said load request and the second tag and the index address of the physical address also included in said load request;
and
an invalidation instructing unit which receives a store request including the physical address, and transmits an invalidation instruction including the index address and the way number based on the second tag of the physical address included in said store request which has been received and the relation state stored in the corresponding state storage unit.

A coherency control method, comprising:

translating a logical address including a first tag, an index address and an offset address of a first storage unit of a set associative system into a physical address of a second storage unit, the physical address including a second tag, the index address and the offset address;
transmitting a load request including at least the physical address and a way number of a way to which an area of the first storage unit designated by the logical address corresponding to said physical address belongs;
storing a relation state between an area of the second storage unit and an area of the first storage unit based on the way number included in the load request which has been received and the second tag and the index address of the physical address also included in the load request which has been received;
and
receiving a store request including the physical address, and transmitting an invalidation instruction including the index address and the way number based on the second tag of the physical address included in said store request which has been received and the stored relation state.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/794,912Filed 7 Jun 2010
Priority: JP 136818/20096 Aug 2009
Published: 10 Feb 2011
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

G06F 12/1072
Address translation: decentralised address translation, e.g. in distributed shared memory systems
G06F 12/0808
Multiuser, multiprocessor or multiprocessing cache systems: with cache invalidating means
G06F 12/0811
Multiuser, multiprocessor or multiprocessing cache systems: with multilevel cache hierarchies
G06F 12/1027
Address translation: using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]