Partitioning a Crossbar Interconnect in a Multi-Channel Memory System

A computer-readable tangible medium storing instructions executable by a computer, the instructions comprising:

• instructions that are executable by the computer to allocate a first set of buffer areas in a multi-channel memory, the first set of buffer areas accessible to a first set of masters via a crossbar fabric;
• instructions that are executable by the computer to allocate a second set of buffer areas in the multi-channel memory, the second set of buffer areas accessible to a second set of masters via the crossbar fabric;
• instructions that are executable by the computer to create a first partition of the crossbar fabric based on the first set of buffer areas;
• and
• instructions that are executable by the computer to create a second partition of the crossbar fabric based on the second set of buffer areas.

An electronic device, comprising:

• a multi-channel memory having a first set of buffer areas and a second set of buffer areas;
• a plurality of masters comprising a first set of masters and a second set of masters, wherein the first set of buffer areas are allocated to the first set of masters, and wherein the second set of buffer areas are allocated to the second set of masters;
• and
• a crossbar interconnect to enable the plurality of masters to access a multi-channel memory, the crossbar interconnect partitioned into a plurality of partitions based on the allocation of the first set of buffer areas to the first set of masters and the allocation of the second set of buffer areas to the second set of masters.

An electronic device, comprising:

• multi-channel memory means for storing data, the multi-channel memory means comprising a first set of buffer areas and a second set of buffer areas;
• bus master means for controlling a bus, the bus master means comprising a first set of bus masters and a second set of bus masters, wherein the first set of buffer areas are allocated to the first set of bus masters, and wherein the second set of buffer areas are allocated to the second set of bus masters;
• and
• interconnect means for enabling the bus master means to access the multi-channel memory means, wherein the interconnect means are partitioned into a plurality of partitions based on the allocation of the first set of buffer areas to the first set of bus masters and the allocation of the second set of buffer areas to the second set of bus masters.

A method, comprising:

• a first step for identifying a first set of masters and a second set of masters from a plurality of masters, the plurality of masters accessing a multi-channel memory via a crossbar interconnect;
• a second step for partitioning the crossbar interconnect into a plurality of partitions comprising at least a first partition corresponding to the first set of masters and a second partition corresponding to the second set of masters;
• a third step for allocating a first set of buffer areas in the multi-channel memory, the first set of buffer areas corresponding to the first set of masters;
• and
• a fourth step for allocating a second set of buffer areas in a second set of buffer in the multi-channel memory, the second set of buffer areas corresponding to the second set of masters.

A method comprising:

• receiving design information representing at least one physical property of a semiconductor device, the semiconductor device comprising:
• a multi-channel memory having a first set of buffer areas and a second set of buffer areas;
• a plurality of masters comprising a first set of masters and a second set of masters, wherein a first set of buffer areas are allocated to the first set of masters, and wherein a second set of buffer areas are allocated to the second set of masters;
• and
• a crossbar interconnect to enable the plurality of masters to access the multi-channel memory, the crossbar interconnect partitioned into a plurality of partitions based on the allocation of the first set of buffer areas to the first set of masters and based on the allocation of the second set of buffer areas to the second set of masters;
• transforming the design information to comply with a file format;
• and
• generating a data file including the transformed design information.

A method comprising:

• receiving a data file comprising design information corresponding to a semiconductor device;
• and
• fabricating the semiconductor device according to the design information,
• wherein the semiconductor device comprises:
• a multi-channel memory having a first set of buffer areas and a second set of buffer areas;
• a plurality of masters comprising a first set of masters and a second set of masters, wherein a first set of buffer areas are allocated to the first set of masters, and wherein a second set of buffer areas are allocated to the second set of masters;
• and
• a crossbar interconnect to enable the plurality of masters to access the multi-channel memory, the crossbar interconnect partitioned into a plurality of partitions based on the allocation of the first set of buffer areas to the first set of masters and based on the allocation of the second set of buffer areas to the second set of masters.

A method comprising:

• receiving design information comprising physical positioning information of a packaged semiconductor device according to the device information, wherein the semiconductor device comprises:
• a multi-channel memory having a first set of buffer areas and a second set of buffer areas;
• a plurality of masters comprising a first set of masters and a second set of masters, wherein a first set of buffer areas are allocated to the first set of masters, and wherein a second set of buffer areas are allocated to the second set of masters;
• and
• a crossbar interconnect to enable the plurality of masters to access the multi-channel memory, the crossbar interconnect partitioned into a plurality of partitions based on the allocation of the first set of buffer areas to the first set of masters and based on the allocation of the second set of buffer areas to the second set of masters;
• transforming the design information to comply with a file format;
• and
• generating a data file including the transformed design information.

A method comprising:

• receiving a data file comprising design information comprising physical positioning information of a packaged semiconductor device on a circuit board;
• and
• manufacturing the circuit board configured to receive the packaged semiconductor device according to the design information, wherein the packaged semiconductor device comprises:
• a multi-channel memory having a first set of buffer areas and a second set of buffer areas;
• a plurality of masters comprising a first set of masters and a second set of masters, wherein a first set of buffer areas are allocated to the first set of masters, and wherein a second set of buffer areas are allocated to the second set of masters;
• and
• a crossbar interconnect to enable the plurality of masters to access the multi-channel memory, the crossbar interconnect partitioned into a plurality of partitions based on the allocation of the first set of buffer areas to the first set of masters and based on the allocation of the second set of buffer areas to the second set of masters.