Pixel sensor converters and associated apparatus and methods

A column sensor for an image sensor array, the column sensor comprising a plurality of pixel sensors, each pixel sensor comprising:

• a modulator of a delta-sigma converter, the modulator configured to be in communication with a detector and configured to sample an analogue signal received from a detector at a particular sampling rate, the modulator further configured to provide a bit stream of a particular bit rate, such a bit stream corresponding to a sampled analogue signal;
• and wherein
• the column sensor comprises a decimator of a delta-sigma converter, the decimator in communication with the modulators of the pixel sensors, the decimator configured to receive and modify serially each bit stream from the one or more modulators in order to provide a digital output signal.

A pixel sensor converter for use with a detector, the pixel sensor converter provided on a semiconductor die, wherein the die comprises circuitry for a modulator, circuitry for a decimator, and capacitors for use with at least one of the modulator and decimator, the die being layered such that the capacitors partially or fully overlap with the circuitry for the decimator or the circuitry for the modulator.

A method of providing for a digital output signal of a pixel sensor, the pixel sensor comprising a decimator configured to provide finite impulse response filtering of a bit stream from a modulator, the method comprising:

• using a sampling rate associated with the modulator of the pixel sensor in order to determine one or more finite impulse response coefficients;
• communicating the one or more coefficients to the decimator in order to allow for providing of a digital output signal.

Apparatus for providing for a digital output signal of a pixel sensor, such a pixel sensor comprising a decimator configured to provide finite impulse response filtering of a bit stream from a modulator, the apparatus configured to use a sampling rate associated with a modulator of a pixel sensor and to determine one or more finite impulse response coefficients;

• the apparatus further configured to communicate one or more determined coefficients to a decimator of a pixel sensor in order to allow for providing of a digital output signal.

A decimator for an image sensor array, the decimator comprising:

• an accumulator configured to modify bits associated with a bit stream received from a modulator at a particular bit rate, the accumulator comprising one or more 1-bit registers, the 1-bit registers configured to modify serially bits so as to provide a digital output signal, such a digital output signal representative of an a received bit stream, but having a reduced bit rate.

A means for decimating for a means for sensing images, the means for decimating comprising:

• a means for accumulating, the means for accumulating configured to modify bits associated with a bit stream received from a means for modulating at a particular bit rate, the means for accumulating comprising one or more 1-bit means for registering, the 1-bit means for registering configured to modify serially bits so as to provide a digital output signal, such a digital output signal representative of a received bit stream, but having a reduced bit rate.