Stacking Technique for Circuit Devices

A circuit device, comprising:

• a combination of a circuit building block (CBB) and a stackable line routing and contact distribution block (CDB), the CBB being stackable and pluggable on the CDB and comprising:
• a device frame including a top face and a bottom face and a plurality of integrated semiconductor circuit device packages arranged on either the top face or the bottom face and complementary mechanical connection elements and electrical connection elements, wherein the complementary mechanical connection elements of the CBB comprise:
• a plurality of first pairs of complementary male and female plug-in engagement elements, either of the male or female plug-in engagement elements of the first pairs respectively arranged at matching opposite positions on the top and bottom face of the device frame and configured to provide a mutual plug-in engagement of male plug-in engagement elements into mating female plug-in engagement elements, and wherein
• the electrical connection elements comprise a plurality of first electrical contact elements arranged on the bottom face of the device frame in predetermined positions and grouped in positional association with each device package, the first electrical contact elements of a respective group being respectively connected to a corresponding package contact of an associated circuit device package, and the first electrical contact elements being configured to provide an electrical connection of signal and power supply lines from the CDB to each of the circuit device packages on the CBB.

A memory device comprising:

• a pluggable first device package accommodating an integrated semiconductor memory die or chip and including mechanical and electrical connection elements, wherein:
• the mechanical connection elements comprise a plurality of at least first male or first female plug-in engagement elements at predetermined positions on a bottom face of the first device package and are configured to provide a mutual corresponding plug-in engagement of the male plug-in elements of the first device package into a plurality of mating female plug-in engagement elements of a second device package or a mutual plug-in engagement of the first female plug-in engagement elements of the first device package into a corresponding plurality of male plug-in engagement elements of the second device package positioned in matching arrangement beneath the bottom face of the pluggable first device package;
• and
• the electrical connection elements are arranged to electrically connect signal lines and power supply lines from the second device package with corresponding signal connections and power supply connections of the semiconductor memory die or chip accommodated within the first device package and comprise a plurality of at least first electrical contact elements arranged in a predetermined arrangement on the bottom face of the first device package and each first electrical contact element being respectively configured to provide an electrical connection to a corresponding matching electrical contact element of the second device package in a state where the pluggable first device package is plugged in and stacked upon the underlying second device package.