Manufacturing method of semiconductor device

#This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2009-183147 filed on Aug. 6, 2009, the entire contents of which are incorporated herein by reference.

#The present disclosure generally relates to a manufacturing method of a semiconductor device.

#Miniaturization of a semiconductor integrated circuit has been advanced according to scaling rules, and a wiring has been miniaturized along with elements of MOS transistors etc. A copper wiring with lower resistance has become a mainstream replacing an aluminum wiring. Patterning copper wiring with high accuracy is difficult. Thus, a damascene wiring is employed in which a recessed portion is formed in an insulating film to bury a wiring. Copper diffusion in an insulating film deteriorates insulating characteristics. Hence, a configuration is employed in which a copper wiring is wrapped, for example, by a barrier metal film or an insulating copper diffusion preventing film. In many cases, a copper wiring layer is formed by plating. A recessed portion for a wiring is formed over an interlayer dielectric film and a barrier metal film, a plating seed layer is formed by sputtering, and a copper layer is formed over the seed layer by electrolytic plating. The barrier metal film has a function to barrier against diffusion of copper atoms from the copper layer, and is formed, for example, with TiN, Ta, Ta/TaN or Ti. The seed layer functions as an electrode for electrolytic plating and as a seed for plating film formation, and formed with copper or a copper alloy. The barrier metal film and the seed layer formed by sputtering are formed over the interlayer dielectric film as well. The plating layer is formed over the seed layer. Unnecessary metal layers over the interlayer dielectric film are removed by chemical mechanical polishing (CMP) and a SiC or SiN insulating copper diffusion preventing film is deposited so as to cover the copper wiring and the interlayer dielectric film. In this manner, sides and a lower surface of the copper wiring formed as described above are covered by the seed layer and the barrier metal film, and the upper surface is covered by an insulating copper diffusion preventing film.

#FIGS. 1A to 1E are sectional views schematically illustrating processes for plating a damascene copper wiring layer in wiring trenches with different widths;

#FIGS. 2A to 2B and FIGS. 2D to 2G are sectional views illustrating processes of a method to manufacture a semiconductor device according to an embodiment;

#FIG. 2C is a graph illustrating change in thickness of a copper layer with time;

#Preferred embodiments will be explained with reference to accompanying drawings.

#In creating a damascene wiring, a wiring trench is formed in an insulating film. A depth of the wiring trench is substantially constant regardless of a wiring width, and an area of a side wall per unit length of a long wiring is substantially constant regardless of a wiring width. A bottom area increases as a wiring width increases. Accordingly, regardless of whether an alloy seed layer is formed by sputtering with directivity process, or Chemical Vapor Deposition (CVD) process that is conformal, influence of a side wall is expected to be larger in a thin-width wiring compared with that of a large-width wiring.

#An amount of the seed layer over the bottom is proportional to a wiring width when the seed layer is formed in a wiring trench with a substantially uniform thickness by the CVD that is conformal film formation. Amount of the seed layer over the side wall is substantially constant regardless of a wiring width. When an additional element in the seed layer over the side wall is redistributed to the entire wiring; a concentration of the additional element of the wiring in the thin-width wiring trench becomes higher than that in the large-width wiring trench.