Method of manufacturing a cmos device with zero soft error rate
AssigneeAvolare 2, LLC
InventorsJohn P. Snyder, John M. Larson
Life of this patent
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Abstract
A CMOS device and method of manufacture is provided for producing an integrated circuit that is not susceptible to various soft errors such as single-event upsets, multi-bit upsets or single-event latchup. The CMOS device and method utilizes a new and novel well architecture in conjunction with metal source/drain electrodes to eliminate soft errors. In one embodiment, the CMOS device uses a first metal source/drain material for the NMOS device and a second metal source/drain material for the PMOS device. The CMOS device further uses a multi-layered well-structure with a shallow N-well and a buried P-well for the PMOS device and a shallow P-well and a buried N-well for the NMOS device.
Claims12
A method of manufacturing a device for regulating a flow of electrical current, the method comprising:
- providing a semiconductor substrate;
- providing a buried N-well in an NMOS active region;
- providing a P-well in the NMOS active region, the P-well disposed vertically above the buried N-well;
- providing a buried P-well in a PMOS active region;
- providing an N-well in the PMOS active region, the N-well disposed vertically above the buried P-well;
- providing at least one of a first gate electrode in the PMOS active region;
- providing at least one of a second gate electrode in the NMOS active region;
- exposing the semiconductor substrate in an area proximal to the first and second gate electrodes;
- providing a first Schottky or Schottky-like source electrode and/or drain electrode that is proximal or overlapped with the first gate electrode;
- and
- providing a second Schottky or Schottky-like source electrode and/or drain electrode that is proximal or overlapped with the second gate electrode.
Dependencies are inferred from the claim text.