Stack package that prevents warping and cracking of a wafer and semiconductor chip and method for manufacturing the same

A method for manufacturing a stack package, comprising the steps of:

• defining a plurality of grooves in an upper surface of a first wafer and a second wafer such that the grooves do not pass through the entire depth of the first and second wafers, wherein the first and second wafers each have a plurality of semiconductor chips and each semiconductor chip has a plurality of bonding pads;
• forming through-silicon vias in the grooves of the first and second wafers;
• forming redistribution layers on the upper surface of the first and second wafers for connecting each through-silicon vias to its corresponding bonding pad;
• attaching the upper surface of the first wafer to the upper surface of the second wafers, such that the corresponding redistribution layers are brought into contact with each other;
• grinding a lower surface of the first and second wafer such that the through-silicon vias formed in the first and second wafers are exposed;
• and
• sawing the attached first and second wafers between the semiconductor chips in the first and second wafers, such that a plurality of package units is formed.