Edge connect wafer level stacking

A method of making a stacked microelectronic package, the method comprising the steps of:

• forming a microelectronic assembly by stacking a first subassembly including a plurality of microelectronic elements onto the adhesive layer of a substrate, at least some of the plurality of microelectronic elements of said first subassembly having traces that extend to respective edges of the microelectronic elements;
• and then
• forming initial notches in said first subassembly so as to expose said traces and coating an adhesive layer on said first subassembly so as to fill said initial notches with adhesive and cover said traces;
• and then
• stacking a second subassembly including a plurality of microelectronic elements onto said adhesive layer of said first subassembly, at least some of the plurality of microelectronic elements of said first subassembly having traces that extend to respective edges of the microelectronic elements;
• and then
• forming initial notches in said second subassembly so as to expose said traces and coating an adhesive layer on said second subassembly so as to fill said initial notches with adhesive and cover said traces;
• and then
• forming notches in the adhesive layers so as to expose the traces of at least some of the plurality of microelectronic elements;
• and forming leads at the side walls of the notches, the leads being in electrical communication with at least some of the traces.