Resource arbitration

Abstract

A circuit includes queue buffers, a bid masking circuit, and a priority selection circuit. Each of the queue buffers carries packets of a respective message class selected from a set of message classes and asserts a respective bid signal indicating that the queue buffer carries a packet that is available for transmission. The bid masking circuit produces a masked vector of bid signals by selectively masking one or more of the bid signals asserted by the queue buffers based on credit available to transmit the packets and on cyclical masking of one or more of the bid signals asserted by ones of the queue buffers selected for packet transmission. The priority selection circuit selects respective ones of the queue buffers from which packets are transmitted based on the masked vector of bid signals produced by the bid masking circuit.

Dependencies are inferred from the claim text.