Input buffer circuit, semiconductor memory device and memory system
AssigneeSamsung Electronics Co., Ltd.
InventorsHyoung-Seok Kim, Kwan-Yong Jin
Life of this patent
Estimating the term…
Abstract
An input buffer circuit includes a logic unit, a clock enable buffer, and a clock buffer. The logic unit is configured to receive a clock signal and a clock enable signal, and to output a decision signal indicative of whether the clock signal is normally input, where the decision signal is activated when the clock signal is normally input. The clock enable buffer is configured to buffer the clock enable signal and to activate an internal clock enable signal, in response to an activation of the decision signal. The clock buffer is configured to buffer the clock signal and to output an internal clock signal, in response to an activation of the internal clock enable signal.
Claims15
An input buffer circuit of a semiconductor memory device, comprising:
- a logic unit configured to receive a clock signal and a clock enable signal, and to output a decision signal indicative of whether the clock signal is normally input, wherein the decision signal is activated when the clock signal is normally input;
- a clock enable buffer configured to buffer the clock enable signal and to activate an internal clock enable signal, in response to an activation of the decision signal;
- and
- a clock buffer configured to buffer the clock signal and to output an internal clock signal, in response to an activation of the internal clock enable signal.
A semiconductor memory device, comprising:
- a memory core unit that includes a memory cell array;
- a buffer unit that includes a plurality of buffers configured to provide an internal address and internal control signals to the memory core unit in synchronization with an internal clock signal;
- and
- an input buffer circuit including:
- a clock enable buffer configured to activate an internal clock enable signal, in response to a clock signal and a clock enable signal, the internal clock enable signal being activated when the clock signal is normally input;
- and
- a clock buffer configured to buffer the clock signal to provide the internal clock signal, in response to an activation of the internal clock enable signal.
A memory system comprising:
- a plurality of memory modules;
- and
- a memory controller configured to generate clock enable signals to each of the memory modules to control an operation of each of the memory modules,
- each of the memory modules including:
- a logic unit configured to output a decision signal indicating whether a clock signal is normally input, in response to the clock signal and the clock enable signal, wherein the decision signal is activated when the clock signal is normally input;
- a clock enable buffer configured to buffer the clock enable signal and to activate an internal clock enable signal, in response to an activation of the decision signal;
- and
- a clock buffer configured to buffer the clock signal to output the internal clock signal, in response to an activation of the internal clock enable signal.
Dependencies are inferred from the claim text.