Sub-word line driver circuit and semiconductor memory device having the same

A semiconductor memory device, comprising:

• a sub-word line driver circuit configured to provide a sub-word line with a sub-word line drive signal in response to a word line enable signal;
• and
• a memory cell array including a plurality of memory cells, each of the plurality of the memory cells being connected to the sub-word line and a bit line,
• wherein the sub-word line driver circuit includes:
• a substrate including a plurality of isolation areas and a plurality of active areas, the two consecutive active areas being separated by each isolation area, the isolation areas and the active areas being extended in a first direction and being arranged in a second direction perpendicular to the first direction;
• a plurality of gate lines formed on the substrate, the gate lines being extended in the second direction and being arranged in the first direction;
• and
• at least one gate tab formed on the substrate, the at least one gate tab being extended in the first direction to cover the isolation area.