Semiconductor memory with multiple wordline selection

A circuit for use with a memory array that comprises a plurality of wordlines each connected to a respective row of cells within a plurality of rows of cells, the circuit comprising:

• a first input for receiving a row signal indicative of selection of a single one of the rows, hereinafter an individually selected row;
• a second input for receiving a preset control signal indicative of selection of a group of rows, hereinafter jointly selected rows;
• circuitry for combining the row signal and the preset control signal to produce, for each of the rows, a respective wordline selection signal, the wordline selection signal for each of the rows being indicative of selection of that row when it is at least one of (i) the individually selected row and (ii) one of the jointly selected rows, and being indicative of non-selection of that row when it is both not the individually selected row and not one of the jointly selected rows;
• an output for releasing the wordline selection signal for each of the rows to the memory array via a wordline driver.