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US 2011/0032781 A1Published application
Memory device and memory control method
AssigneeEtron Technology, Inc.
InventorsChun SHIAH, Shi-Huei Liu
Life of this patent
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Abstract
The embodiments of the present invention disclose a memory device having a fast and shared redundancy decision scheme and a memory control method. The memory device includes an address receiver, a command receiver, a command controller, a row address generator, a column address generator and a shared redundancy decision circuit.
Claims21
A memory device, comprising:
- an address receiver, for receiving and converting external address information to generate internal address information;
- a command receiver, for receiving and converting an external command to generate an internal command;
- a command controller, for generating a row latch control signal or generating a column latch control signal according to the internal command;
- a row address generator, for receiving the internal address information and deciding how to convert the internal address according to the row latch control signal so as to generate a latched row address;
- a column address generator, for receiving the internal address information and deciding how to convert the internal address according to the column latch control signal so as to generate a latched column address;
- and
- a shared redundancy decision circuit, for receiving the internal address information and then either generating a row redundancy start signal according to the internal address information and the row latch control signal or generating a column redundancy start signal according to the internal address information and the column latch control signal;
- wherein, when the row redundancy start signal or column redundancy start signal generated by the shared redundancy decision circuit is at a first voltage level, the memory device starts a normal word line circuit of the corresponding latched row address or starts a normal bit switch circuit of the corresponding latched column address;
- and, when the row redundancy start signal or column redundancy start signal generated by the shared redundancy decision circuit is at a second voltage level, the memory device starts a redundancy word line circuit of the corresponding latched row address or starts a redundancy bit switch circuit of the corresponding latched column address.
6 more elements
A memory device, comprising:
- a memory circuit, for receiving address information and command information to generate a non-latched address, a row latch signal or a column latch signal, and a latched row address or a latched column address;
- and
- a shared redundancy decision circuit, for deciding to start the normal circuit of the row or column or to start the redundancy circuit of the row or the column in advance based on the non-latched address and the row latch signal or the column latch signal, before the latched row address or the latched column address is outputted to the normal circuit of the row or column of a storage unit of the memory device or to the redundancy circuit of the row or the column of a storage unit of the memory device.
A memory control method, comprising:
- receiving address information and command information to generate a non-latched address, a row latch signal or a column latch signal, and a latched row address or a latched column address;
- performing redundancy decision by deciding to start the normal circuit of the row or column or to start the redundancy circuit of the row or the column in advance based on the non-latched address and the row latch signal or the column latch signal, before the latched row address or the latched column address is outputted to the normal circuit of the row or column of a storage unit of the memory device or to the redundancy circuit of the row or the column of a storage unit of the memory device;
- and
- accessing data in the memory based on the normal circuit of the row or the column or the redundancy circuit of the row or the column.
1 more element
Dependencies are inferred from the claim text.