Semiconductor memory device

A semiconductor memory device comprising:

• a first word line;
• a pair of first bit lines;
• a first memory cell connected to the first word line and the pair of first bit lines;
• a first select circuit configured to select one of the pair of first bit lines;
• a write circuit connected via the first select circuit to the pair of first bit lines;
• and
• a power supply voltage detector configured to detect whether or not a power supply voltage is higher than or equal to a predetermined voltage value,
• wherein
• the write circuit includes
• a first control circuit configured to control a potential of the one selected by the first select circuit of the pair of first bit lines to a first potential,
• a second control circuit configured to control the potential of the selected bit line to a second potential which is lower than the first potential, and
• a third control circuit configured to be controlled to a third potential in accordance with an output signal of the power supply voltage detector, and
• the second control circuit and the third control circuit are connected in parallel to each other.

A semiconductor memory device comprising:

• a pair of global bit lines;
• a precharge control signal;
• at least one hierarchical array connected to the pair of global bit lines and the precharge control signal;
• and
• a write array select signal configured to select one of the at least one hierarchical array to which write operation is to be performed,
• wherein
• each of the at least one hierarchical array includes
• a pair of local bit lines,
• a memory array connected to the pair of local bit lines,
• a precharge circuit connected to the precharge control signal and the pair of local bit lines,
• a local bit line select switch configured to select one of the pair of local bit lines, and
• a hierarchical write circuit, and
• the hierarchical write circuit is connected to the write array select signal, and includes a first control circuit including a transistor element, and a second control circuit including a capacitor.

A semiconductor memory device comprising:

• a pair of global bit lines;
• at least one hierarchical array connected to the pair of global bit lines;
• and
• a write array select signal configured to select one of the at least one hierarchical array to which write operation is to be performed,
• wherein
• each of the at least one hierarchical array includes
• a pair of local bit lines,
• a memory array connected to the pair of local bit lines,
• a local bit line control circuit configured to control the pair of local bit lines, and
• a hierarchical write circuit, and
• the hierarchical write circuit is connected to the write array select signal, and includes a first control circuit including a transistor element, and a second control circuit including a capacitor.