Semiconductor memory circuit

A semiconductor memory circuit comprising:

• a first terminal which receives a first control signal;
• a second terminal which receives a second control signal;
• a third terminal;
• a power source terminal which receivers a power source voltage;
• a first input circuit which is coupled to the first terminal and which outputs a first internal signal;
• a second input circuit which is coupled to the second terminal and the power source terminal and which outputs a second internal signal;
• a processing circuit which includes a DRAM circuit and which outputs a data signal in response to the first internal signal;
• an output circuit which receivers the data signal and outputs an output signal to the third terminal;
• and
• a power supply unit which is coupled to the power source terminal and the processing circuit,
• wherein when the second control signal is in the first level, the power supply unit stops supplying an internal voltage to the processing circuit, and when the second control signal is in a second level different form the first level, the power supply unit supplies the internal voltage to the processing circuit,
• wherein when the second control signal is in the first level, the output circuit is in an output high impedance state in accordance with the second internal signal.