Memory circuit and voltage detection circuit including the same

A memory circuit, comprising:

• a first switch provided between a first signal node and a second signal node;
• a nonvolatile memory element of a first conductivity type, including a source connected to a first power supply terminal;
• an inverter;
• a first MOS transistor of a second conductivity type which is controlled to an off state when the data is loaded to and written into the nonvolatile memory element, and controlled to an on state when the data is read, the first MOS transistor including a source connected to a second power supply terminal and a drain connected to the second signal node;
• a second MOS transistor of the second conductivity type which is turned on when a first power supply voltage is input and turned off when a second power supply voltage is input, the second MOS transistor including a gate connected to the second signal node, a source connected to the second power supply terminal, and a drain connected to an input terminal of the inverter;
• a third MOS transistor of the second conductivity type which is controlled to an off state when the data is loaded to and written into the nonvolatile memory element, and controlled to an on state when the data is read, the third MOS transistor including a source connected to the second power supply terminal through a current source and a drain connected to the input terminal of the inverter;
• a fourth MOS transistor of the first conductivity type, including a source connected to the first power supply terminal;
• a fifth MOS transistor of the first conductivity type, including a source connected to a drain of the nonvolatile memory element and a drain of the fourth MOS transistor, and a drain connected to the input terminal of the inverter;
• a first control circuit for controlling the fourth MOS transistor so that the fourth MOS transistor is turned on during loading and is turned off during writing and reading;
• and
• a second control circuit for controlling the fifth MOS transistor so that the fifth MOS transistor is turned off when the first power supply voltage is input during loading, turned on when the second power supply voltage is input during loading, and turned off during writing and reading.