Semiconductor Memory With Improved Memory Block Switching
AssigneeSanDisk 3D LLC
InventorsThomas Yan, Luca Fasoli, Roy E. Scheuerlein
Life of this patent
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Abstract
A non-volatile memory core comprises one or more memory bays. Each memory bay comprises one or more memory blocks that include a grouping of non-volatile storage elements. In one embodiment, memory blocks in a particular memory bay share a group of read/write circuits. During a memory operation, memory blocks are transitioned into active and inactive states. The process of transitioning blocks from an inactive state to an active state includes enabling charge sharing between a memory block entering the active state and another memory block that was previously in the active state. This charge sharing improves performance and/or reduces energy consumption for the memory system.
Claims26
A method for operating a non-volatile storage system, comprising:
- setting a first group of non-volatile storage elements into an active state, said setting a first group of non-volatile storage elements into said active state includes biasing a plurality of first control lines to one or more unselected voltages, each first control line is coupled to a subset of said first group of non-volatile storage elements;
- setting a second group of non-volatile storage elements into an inactive state, each non-volatile storage element of a subset of said second group of non-volatile storage elements is coupled to one of a plurality of second control lines;
- and
- transitioning said second group of non-volatile storage elements from said inactive state to said active state, said transitioning includes sharing charge between said plurality of first control lines and said plurality of second control lines.
A method for operating a non-volatile storage system, comprising:
- decoding a read command from a host;
- identifying a set of memory blocks that contain the requested data to be read;
- setting a first memory block into a read state;
- setting a second memory block into an inactive state;
- reading data from said first memory block;
- transitioning said first memory block into the inactive state and said second memory block into the read state, said transitioning includes sharing charge between said first memory block and said second memory block;
- reading data from said second memory block;
- and
- outputting the data read to said host.
A method for operating a non-volatile storage system, comprising:
- biasing a plurality of first control lines, each first control line is coupled to a respective subset of a first plurality of non-volatile storage elements;
- floating a plurality of second control lines, each second control line is coupled to a respective subset of a second plurality of non-volatile storage elements;
- and
- setting up read conditions for said second plurality of non-volatile storage elements, said setting up read conditions includes sharing charge between said plurality of first control lines and said plurality of second control lines.
A non-volatile storage system, comprising:
- non-volatile storage elements including a first set of said non-volatile storage elements and a second set of said non-volatile storage elements;
- a plurality of first control lines, each first control line is coupled to a respective subset of said first set of non-volatile storage elements;
- a plurality of second control lines, each second control line is coupled to a respective subset of said second set of non-volatile storage elements;
- and
- a charge transfer circuit coupled to both said plurality of first control lines and said plurality of second control lines, said charge transfer circuit comprises a first switch, said first switch controls charge sharing between said plurality of first control lines and said plurality of second control lines while setting up read conditions for said second set of non-volatile storage elements.
A non-volatile storage system, comprising:
- a first memory block comprising a plurality of first control lines, said first memory block set into a read state;
- a second memory block comprising a plurality of second control lines, said second memory block set into an inactive state;
- and
- a charge transfer circuit coupled to both said plurality of first control lines and said plurality of second control lines, said charge transfer circuit controls charge sharing between said plurality of first control lines and said plurality of second control lines during a transitioning of said second memory block from said inactive state into said read state.
Dependencies are inferred from the claim text.